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Q3 2008    
Editor's Words

CDNLive! Speakers Address a New Vision for Design

CDNLive! Silicon Valley 2008 kicked off Tuesday with keynotes by Cadence executive vice president and CTO, Ted Vucurevich, and University of California at Berkeley Distinguished Professor, Jan Rabaey. A panel entitled “Low Power, Green Power and the Future of IT” also brought together experts to address issues related to creating energy-efficient devices, and the need to protect the Earth's climate and conserve its resources. Read Details»

On 09 Sep 2008, Cadence announced the availability of its software as a service (SaaS) offerings for semiconductor design. These production-proven, ready-to-go design environments are accessible via the Internet and provide design teams a faster time-to-productivity with reduced risk and cost. Cadence Hosted Design Solutions are available for custom IC design, logic design, physical design, advanced low power, functional verification, and digital implementation.
News | Overview | Datasheet

Power Forward Initiative (PFI) today announced that Wipro Technologies has recently joined the initiative and is offering Common Power Format (CPF)-enabled low-power design capabilities to its design services customers worldwide. The PFI membership has now grown to over 30 companies around the world, representing a broad spectrum of semiconductor, IP, EDA, ASIC, design services and manufacturing providers. Read Details»

 
In the News
  • Cadence Expands Enterprise Verification Solution to Include Planning, Unified
         Verification Metrics and Industry Databases»
  • Cadence Extends Low-Power Leadership With Early Dynamic Power Analysis
         and Pre-RTL Exploration»
  • Cadence Encounter Power System Delivers Next-Generation Power Integrity
         and Signoff Analysis for Advanced Node Design»

  •      For more…
     
    Success Story
    Fujitsu Automates Standard Cell Migration Using
    Cadence Virtuoso Layout Migrate


    Design Challenge
    -Modify and migrate a library of 177 standard cells in order to create a lower-power library within one month
    -Improve the efficiency of analog design process




     Read Full story»

    Cadence and Accent Companies Validate
    Low-Power Design Techniques from
    Architecture Through Implementation to Enable 40%
    Power Reduction

    Design Challenge
    -Consumer products such as laptops, cell phones, etc., require ever-longer battery life and ever-higher performance, making power management a critical design issue
    -At 90nm and below, increased leakage can mean that devices consume as much power when they are not in use as when they are being used
    -Customers require proven low-power solutions, including physical IP
    -Need a robust design flow that enables correct physical implementation and timing sign off for low-power designs



     Read Full story»