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Q1 2009    
Editor's Words

We have just been notified by EDN that C-to-Silicon Compiler and Incisive Palladium Dynamic Power Analysis are finalists for EDN’s 19th Annual Innovation Awards! Read Details»

Every December, EDN Magazine editors decide on the Hot 100 Electronic Products released that year. This year, the new Cadence® C-to-Silicon Compiler high-level synthesis solution made the list. Read Details»

04 Feb 2009,Cadence announced that the ChipEstimate.com IP ecosystem has been recognized with a DesignVision Award by the International Engineering Consortium (IEC). Read Details»
Watch video | About ChipEstimate.com

 
In the News
  • Cadence Incisive Verification IP Portfolio Delivers 'All-in-One' Flexibility and
         Higher Value for SoC Developers»
         Portfolio Offers OVM Multi-Language Support with Metric-Driven and
       Assertion-Based VIP Under a Single License

  • Customer Testimonials for Semiconductor IP Added to ChipEstimate.com»
         Candid User Comments to Provide Valuable Information on Design and
        Verification IP
  • Cadence Unveils Next-Generation Parallel Circuit Simulator for the
         Verification of Complex Analog and Mixed-Signal IC Designs»
         Virtuoso Accelerated Parallel Simulator Delivers Exceptional Performance
        for Most Challenging Circuit Simulation Tasks, with Full Spectre Accuracy

  •      For more…
     
    Success Story
  • Cadence End-to-End Design Solutions Enable UPEK to Consolidate Seamless Full-Chip Design Flow»
    "By adopting these complete solutions from Cadence, we are able to achieve a seamless design flow, the ease of integration among Cadence tools allows us to reduce time-to-market so as to accelerate challenging chip designs for consumer and industrial products. The consolidation also allows us to focus resources on silicon-based technology and application innovations and boost overall engineering productivity."
    ----Keng-Soon Yap, director of the Singapore Design Center
  • Cadence Low Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design»
    “Using the CPF-enabled Cadence Low-Power Solution, Fujitsu was able to raise the bar on our latest low-power design, with more power saving and reduced turnaround time. This is a proven solution for us, and we will continue to deploy it for other low-power designs.” -----Fujitsu Microelectronics Limited
    Read Full Story | Press Release
  • Hot Topic
  • It is well known that micro-architectural decisions can have a large impact on power consumption. Unfortunately accurate enough estimates of power often emerges too late for an RTL designer to be able to make architectural changes. «The Micro-architecture Power Tradeoffs at the Electronic System Level» describes how Electronic System Level(ESL) compiler technology was used in conjunction with chip estimation techniques to analyze area vs. power tradeoffs at the system architecture development stage. Read Complete Paper»