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Q1 2009
Editor's Words
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| Success Story |
Cadence End-to-End Design Solutions Enable UPEK to Consolidate Seamless Full-Chip Design Flow»
"By adopting these complete solutions from Cadence, we are able to achieve a seamless design flow, the ease of integration among Cadence tools allows us to reduce time-to-market so as to accelerate challenging chip designs for consumer and industrial products. The consolidation also allows us to focus resources on silicon-based technology and application innovations and boost overall engineering productivity."
----Keng-Soon Yap, director of the Singapore Design Center
Cadence Low Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design»
“Using the CPF-enabled Cadence Low-Power Solution, Fujitsu was able to raise the bar on our latest low-power design, with more power saving and reduced turnaround time. This is a proven solution for us, and we will continue to deploy it for other low-power designs.” -----Fujitsu Microelectronics Limited
Read Full Story | Press Release |
| Hot Topic |
| It is well known that micro-architectural decisions can have a large impact on power consumption. Unfortunately accurate enough estimates of power often emerges too late for an RTL designer to be able to make architectural changes. «The Micro-architecture Power Tradeoffs at the Electronic System Level» describes how Electronic System Level(ESL) compiler technology was used in conjunction with chip estimation techniques to analyze area vs. power tradeoffs at the system architecture development stage. Read Complete Paper» |
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