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Q3 2009    
Editor's Words

Cadence showcased a variety of innovative solutions highlighting the company’s technology leadership at the 46th annual Design Automation Conference (DAC), July 26-31 in San Francisco. In collaboration with customers and ecosystem partners, Cadence demonstrated these innovations in multiple venues, emphasizing the depth and breadth of its industry-leading focus on methodologies and solutions that support design projects in both leading edge and mainstream process technologies. Read Details»

Dr. Alberto Sangiovanni-Vincentelli received the 2009 IEEE/RSE Wolfson James Clerk Maxwell Award for his pioneering research in the field of electronic design automation (EDA). Read Details»
In the News
  • Cadence Achieves First-Silicon Results on 32nm Common Platform™
  • Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference
          Flow 10.0»
  • Cadence Introduces First TLM-Driven Design and Verification Solution to
         Increase Engineering Productivity over RTL-based Flows»

  •      For more…
    Success Story
  • Hitachi Implements 50-Million Gate Design Using Cadence Encounter Digital Implementation System»
    Complex, Large-Scale Design is Fully Implemented in Five Weeks
    Read Full story
  • Cadence and Xilinx Simplify SoC Development with Enterprise Verification Capabilities for FPGA Targeted Design Platforms»
    IEEE-Standard Encryption for SecureIP Models Offers 2X Performance Boost; Open Verification Methodology (OVM) to Increase Schedule Predictability and Quality
    Read Full story»
  • Hot Topic
  • Cadence® Encounter® Conformal® ECO Designer enables designers to implement RTL engineering change orders (ECOs) for pre- and post-mask layout. It combines automatic ECO analysis and design netlist modification with world-class equivalence checking to provide superior performance,productivity, capacity, and ease-of-use.
      Read the Datasheet»