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Q4 2009    
Editor's Words
Cadence is bringing its Silicon Valley-based CDNLive! user forum to designers worldwide through a unique combination of live on-site and online customer presentations, workshops and tutorials.

The theme of this year’s conference is Energize! Guests who register for CDNLive! Silicon Valley online can utilize the efficiency of the Internet to interactively learn about the latest methodologies and support for emerging design projects at both leading-edge and mainstream process technologies. Read Details»

Cadence is celebrating Innovation Day, honoring the contributions Cadence® employees have made to the company and the electronics industry as a whole. Having garnered more than 800 U.S. patents and an additional 150 international patents, Cadence has a long legacy of technology innovation that has enabled EDA customers to successfully create some of the world’s most recognized consumer and business products for over 20 years.Read Details»
In the News
  • IC Package Designers Boost Productivity with New Cadence Allegro SiP and IC
         Packaging Software»
       New Software Release with Co-Design and Design Chain Enablement
       Technology Helps Engineers Shorten Design Cycles through Improved Design
       Miniaturization Capabilities
  • Cadence Leverages New Miniaturization Capabilities to Advance PCB Design
       Latest Release of Allegro and OrCAD PCB Software Boosts Productivity and
       Performance While Reducing Design Cycle Time
  • Cadence Introduces Incisive Enterprise Verifier, Delivering Dual Power of
         Formal Analysis and Simulation Engines»
       New Integrated Solution Increases Return on Investment from Assertion-
       Based Verification and Eases Adoption for Design and Verification Engineers
       (Click for video of IEV product announcement.)

  •     For more…
    Success Story
    Cadence Incisive Verification Management Solution Enables Fujitsu Microelectronics Solutions to Achieve Aggressive Verification Goals
    Simpler Verification Planning and Management Process with Automated Metric-Driven Flow Improve Productivity and Predictability for SoC Validation
    Read Full story»

    Constraint-Driven High-Density Interconnect (HDI) PCB Design Flow Helps NVIDIA Speed Products to Market
    Watch the Success Video»
    Read Full story»
    Download Success Story»
    Hot Topic
    As more micro-electro-mechanical systems (MEMS) are being used for automotive and consumer electronics, engineers need a robust MEMS and mixed-signal co-design flow that enables both system-on-chip (SoC) and systemin-package (SiP) approaches. A clear-cut interface between a MEMS design subflow and the conventional mixed-signal sub-flow is necessary. Cadence® VCAD Services has developed an IP for handling the special requirements for a MEMS methodology (for both SoC and SiP applications) called SIMPLI. The IP ensures efficient handling of concurrent design/optimization of the MEMS and electronics while handling engineering change orders between the two domains.
    Read OVERVIEW»