Registration for this year’s CDNLive! Silicon Valley event is now open. Encourage your customers to take advantage of our early-bird registration offer. If they register by September 26, they will receive a complimentary pass. Registrations received after September 26 will be at a rate of $250USD.

Space is limited, so tell your customers to reserve their spot now! They don't want to miss out on this year’s jam-packed event, slated for October 26 at The Fairmont San Jose followed by an optional day of techtorials on October 27 at the Cadence campus! It’s a great chance for them to network with other Cadence technology users, swap ideas on tackling critical design and verification issues, and discover the latest techniques for realizing advanced silicon, SoCs, and systems.

Visit the CDNLive! conference microsite for more details.

Cadence Tech Forum Singapore 2010
Over 200 designers and design managers attended Cadence Tech Forum Singapore 2010 on 25 Aug 2010 to get the latest technology trend and solutions for electronics and semiconductor designs. After Choo Han Seow, Sales Director of Cadence Singapore, kicked off the event, Andreas Kuehlmann, Cadence Fellow and Director of Cadence Research Laboratories, gave a keynote address on “EDA 360 and open integration platform with integration-optimized IP: The Way Forward for Electronic Design” laying out the Cadence vision for the global EDA industry to migrate from productivity to profitability. The attendees joined three breakout sessions on “Custom Design”, “Digital IC Design and Verification” and “System and IC Packaging” to learn the latest Cadence solutions addressing the design challenges they face, such as IP integration, mixed signal, low power, DFM and SiP.

New UVM Book—Available NOW!

Check out this video interview with UVM Book authors Sharon Rosenberg and Kathleen Meade. The Universal Verification Methodology (UVM) is an emerging standard being developed by Accellera. It is based on a simple script conversion of the Open Verification Methodology (OVM) 2.1.1 and thereby inherits the quality and experience of ten years and thousands of successful verification projects. A Practical Guide to Adopting the Universal Verification Methodology, by Sharon Rosenberg and Kathleen Meade provides both, cookbook-style examples for novices and in-depth verification information including system-level verification, sequences for layered protocols, and register package use for expert verification engineers. The book also includes information on using transaction level modeling to interface SystemVerilog, e, and SystemC components together into a cohesive verification environment.