Michael A. Catrambone - Steering Committee Chairman Distinguished Engineer PCB/Mechanical UTStarcom, Inc. Michael Catrambone has over 19 years experience in designing complex printed circuit boards, administering EDA systems/software, creating EDA automation programs and a Cadence trainer of Allegro. He currently develops printed circuits board and associated mechanical components for Wireless and Wireline infrastructure products for the telecom industry. Michael joined UTStarcom through its acquisition of CommWorks Corporation a subsidiary of 3Com Corporation. Prior to CommWorks, Michael worked for USRobotics developing carrier class remote access equipment and Automated Systems, Inc. design service bureau developing printed circuit board boards for military applications for Westinghouse, Northrup Grumman, Raytheon, Lockheed and Martin Marietta to name a few.
		Samta Bansal Sr. Product Marketing Manager Digital implementation Platform Cadence Design Systems, Inc. Samta Bansal is currently Sr. Product Marketing Manager in the Digital implementation Platform at Cadence. Samta joined Cadence in July 2004 as Application Consultant and helped establish Encounter Test in the marketplace in key accounts after the technology acquisition from IBM. Prior to Cadence, Samta was a Product Engineer and then consultant at Synopsys responsible for TetraMAX and DFT Compiler. With hands on experience of Front end for 8 years and moving to Back end, Samta has a good understanding of the evolution and challenges the industry has been going through in terms of solutions. Samta has Masters in Physics, Bachelors in EEE from BITS, Pilani and MBA from Santa Clara University.
		Thomas P. Beckley Corporate Vice President, Research and Development Custom IC Design Cadence Design Systems, Inc. Tom Beckley (Pittsburgh, PA) is the Corporate Vice President of R&D for Cadence's Virtuoso platform design enviroment. Tom manages multiple product lines - Virtuoso Schematic Editor L/XL, Virtuoso Analog Design Environment L/XL/GXL, Mixed-Signal Parasitic (Re)Simulation, NeoCircuit, Virtuoso Specification-driven Environment, etc. He also manages Cadence's Central Architecture and Technology (CAT) team which provides software platforms, widgets, formats and subsystems used throughout Cadence. Tom joined Cadence in 2004 via the Neolinear acqusition where he served as President and CEO. At Neolinear, Tom applied his twenty five years of experience in the semiconductor and business management to quickly establish the company as the leading developer of innovative auto-interactive and automated analog/RF tools/solutions for mixed signal design. Prior to Neolinear, Tom was Head of the Systems Division at Avant! Corporation. Previous to Avant!, Beckley was President and CEO of Xynetix Design Systems, the market leader in advanced IC packaging and systems-level virtual prototyping electronic design software. Prior to Xynetix, Beckley held management positions at Harris Corporation (semiconductor business unit) and General Motors. Tom received his bachelor's degree in physics and applied mathematics from Kalamazoo College and a master's degree in business administration from Vanderbilt University.
		Steven Carlson VP Product Marketing Cadence Design Systems, Inc. Steve is VP of Marketing in the Encounter platform. Steve joined Cadence in April 2003 via the Get2Chip acquisition, where he was the VP of Marketing. Prior to Get2Chip, Steve was the CEO of Tharas Systems, a hardware acceleration company. Steve has also held various management positions at Escalade, LSI Logic, United Technologies and Synopsys. At Synopsys, Steve was a part of the original Design Compiler technical team responsible for timing analysis and optimization. Steve was the author of the industry's first book on high-level design titled, Introduction to HDL-based Design Using VHDL. Steve has BSEE and BSCS and an MSEE all from the University of Colorado.
		Charlie Davies Principle ECAE Application Engineer Harris Corporation Charlie Davies is the principle ECAE application engineer at Harris Government Communications Systems Division. He has over 35 years of experience in PCB Design and manufacturing. For the last 25 years, he has been the principle architect of the PWB design environment at Harris. Charlie has authored and presented numerous papers at the Cadence User Group.
		Stylianos Diamantidis Managing Director Globetech Solutions Stylianos Diamantidis is the Managing Director of Globetech Solutions. Prior to co-founding Globetech Solutions, Stylianos managed SGI?s systems diagnostics group, spanning across servers, supercomputers, and high-end graphics product lines. His current areas of interest include advanced design verification methodologies, embedded systems, silicon test, debug and diagnosis. Stylianos holds a BEng from the University of Kent at Canterbury, UK and a MS in Electrical Engineering from Stanford University, USA.
		Laurent Ducousso Verification Manager of the Home Video Division STMicroelectronics Laurent Ducousso has 20 years of experience in Digital Design and Verification. He joined STMicroelectronics in 1994 as a verification expert, and has since worked on CPU , microcontroller, and DSP projects. Since 2000, he has managed the Home Entertainment Group Verification Team. Prior to STMicroelectronics, he contributed to CPU mainframe development at Bull S.A. for 8 years. Laurent Ducousso holds a PhD in computer sciences from Paris, France.
		Nigel Foley Director of Development Technologies SiRF Technology, Inc. Nigel Foley has over 12 years experience with various CAD areas including digital, analog, mixed signal, RF and modules. In his current role, he leads teams responsible for enabling high quality and optimum design cycle time for mixed-signal, RF IC's and modules. This includes standardization of CAD methodologies across SiRF and resolving unique challenges associated with large mixed-signal and high frequency designs. Nigel holds a B. Eng degree in Computer Engineering from the University of Limerick, Ireland.
		Wolfgang Grimm Senior Principal CAD System Innovation Qimonda AG Wolfgang Grimm has more than 20 years experience in full custom memory design. His expertise encompasses the entire flow, from CMOS design to layout post-processing/RET measures, board and package development. Wolfgang started in 1982 with Siemens R&D, where he was a pioneer in setting up and using automated design flows. In 1987, he joined the memory business group and championed the use of EDA solutions for design development. There he gathered ample experience in all areas of full custom design. Currently, Wolfgang is responsible as technical lead for the CAD setup of Qimonda's* memory technologies, from 110nm down to 40nm, and several flash technologies, including chip-board-package codesign environment. Wolfgang has a strong technical focus on RET (resolution enhancement techniques), a key enabler for current and future technology nodes. * Qimonda was formed as a memory-making spinoff from parent Infineon Technologies AG through an IPO in August 2006.
		AJ Incorvaia VP Research & Development Cadence Design Systems, Inc. AJ Incorvaia is currently Vice President of R&D for the Silicon-Package-Board group at Cadence Design Systems. He leads a worldwide organization of more than 150 engineers responsible for development of printed circuit board design, IC packaging and signal integrity analysis software. AJ has been with Cadence for more than seven years and has over 18 years of experience developing and using EDA tools for systems and IC package design. Prior to joining Cadence, AJ held development and management positions at Digital Equipment Corporation and Viewlogic Systems. While at Viewlogic, he was responsible for the development of front-end design, virtual prototyping and data management solutions. AJ has a BS in Computer Science from Rochester Institute of Technology and a Master's Degree in Software Systems Engineering.
		Senthil Krishnasamy Director, Physical Design AMD Senthil Krishnasamy is Director of Physical Design in the ASIC Services and Technology Group at AMD (formerly ATI). In this role, Senthil leads teams responsible for the physical design of discrete graphics, chipset, handheld, and DTV chips. His organization also works collaboratively with other physical design teams to develop next generation CAD flows and methodologies used across the company. Previously at AMD, Senthil managed the team responsible for the physical design of the XBOX 360 GPU. Prior to joining AMD in 1998, Senthil was a senior test engineer at Celestica Inc where he designed testers and test applications. Senthil holds a bachelors degree in electrical engineering from the University of Waterloo.
		Paul Little Sr. Manager, SoC Design Engineering Center Fujitsu Microelectronics America, Inc. Paul Little is a Sr. Manager in the SoC Design Engineering Center at Fujitsu Microelectronics America, where he leads a team responsible for technical support of Fujitsu's ASIC and foundry products. Prior to this, he was responsible for CAD tool and design methodology development and support. Paul has more than 13 years of experience in the semiconductor industry and during his time at Fujitsu has worked on a wide range of projects, including several ASIC designs, cell library design, and the development of an Internet-based design environment. Prior to Fujitsu, Paul worked as a product engineer for NEC Electronics in Livingston, Scotland, focusing on DRAM wafer and die-level failure analysis. Paul holds a Bachelors degree in Electronic and Electrical Engineering from Heriot Watt University in Edinburgh and a Masters degree in Microelectronics from Brunel University in London.
		Kevin Locker Design Engineer NXP Semiconductors Kevin Locker has over 25 years of digital design and verification experience in areas such as ARM-based SoCs, wired and wireless connectivity IP, fault-tolerant avionics systems, and optical disk drives. Kevin has been with NXP since 2000 and has developed SystemC and C-based verification environments for connectivity products such as PCI-Express, Bluetooth, and Ethernet. Prior to joining NXP, Kevin was a Sr. Staff Engineer at Honeywell International in the ASIC Center of Excellence were he led a team of design engineers working on various commercial avionics-related ASIC and FPGA projects. Kevin holds a Bachelor of Science degree in Electrical Engineering and a Masters of Science in Computer Science from Arizona State University. Kevin has authored 7 patents related to digital design and software algorithms.
		Ed Lutz CAD Support Engineer Motorola Ed Lutz has 20 years experience in designing printed circuit boards and developing EDA solutions and integrations. He is currently a CAD Support Engineer for Motorola in the Motorola Engineering Tools and Solutions (METS) group. The METS team provides best-practices hardware development solutions, incorporating both business and factory DFM requirements. Prior to joining Motorola, Ed worked for Cadence and Automated Systems, Inc. as a service bureau manager and designer of complex commercial and military printed circuit boards. Ed received his bachelor's degree in Business and Computer Science from Ursinus College and is an IPC Certified Interconnect Designer.
		Paul Margozzi Director of CAD and Design Automation Intersil Corporation Paul Margozzi is currently the Director of CAD and Design Automation at Intersil Corporation. His responsibilities span the CAE / CAD infrastructure as well as support for all Design and Layout groups in the US West Coast, UK and India. Additionally he has responsibilities for the Analog Mixed Signal Layout group that produces a large array of amplifiers, analog front ends, communication interfaces, data converters, display solutions, DSL solutions and optical storage products. Prior to Intersil Paul was with other Analog and Mixed-Signal Semiconductor where he was also responsible for CAE / CAD as well as a complete new product development department producing Power Management products and temperature sensors. He spent over a decade at National Semiconductor in the Interface Products R&D group where he developed modeling extraction software and hardware in the early days and then moved onto CAE/CAD when the industry was in its infancy in the mid 80's. Paul has over 26 years experience in Analog and mixed signal product development, centered around the CAE and CAD aspect.
		Herve Menager Architect - SoC Design Technology NXP Semiconductors Herve Menager is with the Chief Technology Office at NXP Semiconductors. As Design Technology Architect, he is responsible for the SoC Design environment for the latest Technology nodes. He also contributes on large SoCs for the consumer market with a focus on advanced design techniques. Prior to Philips, he has held a variety of positions in the physical Design ranging from engineering manager responsible for the development of floorplanning and routing technology at Compass Design Automation (VLSI Technology) to methodology engineering at Aristo Technology. Herve holds a MSEE and graduated from ENSEEIHT (Ecole Nationale superieure d'electronique, electrotechnique, informatique et hydraulique de Toulouse) Institute National Polytechnic of Toulouse.
		Nicolas Perrier Mixed Signal CAD Engineer PMC Sierra Nicolas Perrier is Mixed Signal CAD Engineer at PMC Sierra, member of the Technology Access team that provides technology data, design methodology development, and EDA software needs to the global Mixed Signal Group. Prior to PMC Sierra, Nicolas worked as Engineer, Design for Manufacturing tools at PDF Solutions, where he was responsible for the development of a tool for the automated LVS verification of Characterization Vehicles, a core component of PDF's yield ramping methodology. Prior to PDF solutions, Nicolas was an IC CAD engineer at Mosaid Technologies where he was part of a team developing 'Process Independent Setup' for rapid and automated technology file and ruleset creation. Nicolas holds a Bachelors degree in Computer Engineering from the University of Ottawa School of Information Technology and Engineering
		Francois Rémond Director, CAD & Design Methodology STMicroelectronics - HED Group Francois Rémond is with the Home Entertainment and Displays group at STMicroelectronics, responsible for the SoC Design Methodology and CAD support, covering design activities in US, France, UK and India. He has been involved in IC design since 1982, and is focusing since 12 years on design methodology for large hierarchical System On Chips for, as Set-Top-Boxes and IDTV circuits, using latest technology nodes. Francois holds a Master Degree in Electronics from National Institute of Applied Sciences (INSA 1979).
		Sue Strang Senior Engineer IBM Sue Strang is a member of the Semiconductor Research and Development Center in Essex Junction Vermont where she is a member of the team developing Device Models and Process Design Kits for IBM's BiCMOS, CMOS, RF-CMOS, SiGe, and SOI technologies. Sue has 15 years experience in CAD development at IBM, prior experiences include DRAM and DPS design teams, Reliability and satellite control and telemetry system designs. Sue has received her electrical engineering degrees from the University of Pittsburgh.
		Michael Stellfox Principal Verification Solutions Architect Cadence Verification Division Cadence Design Systems, Inc. Mr. Stellfox is the technical leader of the Cadence verification solutions architecture team. His primary charter is to understand customer verification challenges in order to drive the requirements for developing Cadence verification solutions. In his role, he also works closely with customers and the verification field organization to help develop and deploy verification methodology. Mr. Stellfox joined Cadence in April 2005 as Group Director of the Verification Technical Field Organization. He came to Cadence through the acquisition of Verisity, where he had served many roles, from a verification consulting engineer to Vice President of Consulting Engineering. Prior to joining Verisity, Mr. Stellfox started his EDA career at Viewlogic, where he worked for 5 years as an applications engineer. Mr. Stellfox began his career at IBM, where he worked for 5 years as an ASIC design engineer responsible for designing and verifying a variety of 2D and 3D graphics systems.
		Chuck Tomiello EDA Manager Texas Instruments, Inc. Chuck Tomiello has over twenty years of experience in the semiconductor industry. Chuck started out doing digital IC design in the Defense Systems and Electronics group and later transferred into the Mixed Signal Products group where he implemented standardization of PDK's (process delivery kits) for internally developed schematic and layout capture systems. He was technical lead for the MSP EDA team deploying Cadence 4.3.2/4.3.4 software support for the first Cadence Mixed Signal Products design project at TI. Currently, Chuck is responsible for managing the Dallas EDA team which provides application support and development for High Performance Analog and High Volume Analog designers. Chuck holds a B.S.E.E. from the University of Arkansas and an M.B.A from the University of Dallas.
		Mike Veal Electronics Design Engineer IBM Mike Veal has worked in IBM Storage for 9 years as an electronics design engineer. The work is mainly high speed digital, producing RAID adaptors, but his team has worked on designs from display cards to high current power supplies. Before IBM Mike worked as a product quality engineer for four years for another storage system manufacturer. Whilst not at his desk, Mike enjoy paragliding, caving, kayaking and tinkering with his home built car.
		Ted Vucurevich CTO Cadence Design Systems, Inc. Ted Vucurevich serves as a Cadence Chief Technology Officer, reporting to Michael J. Fister, President and CEO. He is responsible for driving advanced research and development and directing Cadence Laboratories. In addition, he serves as an executive fellow. In his prior role as chief architect at Cadence, Vucurevich helped develop the strategies and technology initiatives in system-on-a-chip (SoC)-based design, DSM infrastructure, software interoperability, design methodology development, and Internet-based electronic system design. Vucurevich joined Cadence in 1992 as director of the Analog Physical Design group. In 1994 he was promoted to work as an architect in the Viper Development group. He was later named chief architect and held that position for five years. Prior to Cadence, Vucurevich worked 14 years at Analog Devices where he held roles in product, design, and computer-aided design (CAD) engineering. He was a co-founder of the Linear Signal Processing Division, where he was responsible for the implementation of a complete mixed-signal ASIC CAD environment. Vucurevich received his bachelor of science degree in electrical engineering from the University of Arizona.