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Logic and Physical Synthesis
In logic and synthesis, we focus on topics in sequential circuit optimization. We're especially interested in retiming and clock skew scheduling. Retiming is a structural transformation that moves the registers in a circuit across the combinational gates. Clock skew scheduling preserves the structure of the circuit but adjusts the latency of the clock signal at the individual registers.
Our research centers around an integrated sequential synthesis flow from RTL to layout that addresses the practical shortcomings of previous work in this area and allows us to take full advantage of the existing optimization potential. For this, we consider not only improving the circuit performance, but also area and power consumption.
Projects
 | Placement | | Logic Synthesis | | Clock Tree Synthesis |
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