International Test Conference (ITC)
| Type: | Conference & Exhibition | | Date: | October 24 - 26, 2006 | | Location: | Santa Clara, CA - Booth #730 | | | Register |
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Overall description
International Test Conference is the world's premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. More »
What you will see
- Presentations by successful Encounter® Test users
- Product demonstrations exhibiting the latest technologies and capabilities found in Encounter Test
- Cadence technologists and experts sharing the latest in test technology
- How to lower the cost of test, increase product quality, and achieve high yield silicon
Tuesday, October 24
2:00pm — 2:30 pm
SESSION B2.1
Corporate presentation: Higher Quality Silicon, Lowered Test Costs and Faster Yield Ramp
Wednesday, October 25
8:30am — 10:00am
SESSION 8
Compression Diagnostics
T. Bartenstein, Cadence Design Systems (Chair)
B. Keller, Cadence Design Systems (Coordinator)
SESSION 10
XJTAG X 3
C. Barnhart, Cadence Design Systems (Chair)
W. Eklow, Cisco Systems (Coordinator)
Wednesday, October 25
4:00pm — 5:30pm
Panel 7 Role of Test in Yield-Learning for 65 nm and Beyond
P. Nigh, IBM (Moderator)
S. Taneja, Cadence Design Systems (Organizer)
The panel will explore yield challenges at and below 65 nm and yield ramp minimization. How can DFT/ATPG/diagnostics be most effectively used? What synergy is possible by integrating test and yield management solutions? A panel of cross-industry leaders will examine the issues that have direct impact on the role of test in yield-learning.
Panelists: M. Campbell, Qualcomm; T. Ho, Credence Systems; R. Segers, NXP Semiconductors; S. Taneja, Cadence Design Systems
Thursday, October 26
8:30am — 10:00am
SESSION 21
Using DFT Techniques In Testing and Design
M. Vachon, Cadence Design Systems (Chair)
R. Raina, Freescale Semiconductor (Coordinator)
SESSION 24
Advances in Validation and ATPG
S. Bhatia, Cadence Design Systems (Chair)
P. Varma, Blue Pearl Software (Coordinator)
Who should attend
- Test, verification, yield, RTL design engineers and management
Questions about this event?
Send email to events@cadence.com Register
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