SEMICON West 2008
| Type: | Conference and Exhibit | | Date: | July 15 - 17, 2008 | | Location: |
Moscone Center, San Francisco, CA
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SEMICON West is the premier electronics industry trade show. Companies from
around the world display technologies that will deliver the future of micro-
and nanoelectronics from design through manufacturing. Learn about the latest
developments in semiconductors, MEMS, renewable energy applications, semiconductor
test, advanced packaging, wafer processing and more from the industry's leading
technologists. New this year, Cadence—the premier Electronics Design Automation
provider—will not only attend but will also have a major presence in a keynote,
panels, presentations, as well as a booth. Experience everything that SEMICON
West has to offer—don't miss it!
Come see us - booth #2147 South Hall
Keynote
Moore Demands, Murphy Blocks, We Deliver, Consumers Benefit!
Speaker: Jim Miller, Executive Vice President, Product and Technologies Organization
July 17, 2008, 10:00am - 10:45am
West Hall, Level 2
TechXPOT Panel
Lithography for 22nm: Will We Have a Viable Solution - and Will We Be Able to Afford it?
Speaker: Richard Brashears, Corporate Vice President
July 15, 2008, 3:00pm - 5:00pm
TechXPOT Presentation
Double Patterning: Are Your Ready?
Speaker: Milind Weling, Engineering Director
July 17, 2008, 11:00am - 1:00pm
Exhibit
July 15-17, 2008
Booth # 2147 South Hall
Products/Technologies Demonstrations
Process and Proximity Compensation - Accelerating Layout-to-Mask-to-Wafer Flow
Traditional OPC / RET tools perform optical correction at various process
points separately. As a result, the time-to-results and quality of
results both suffer. With the fourth generation of OPC tools, Cadence
has revolutionized this critical step in manufacturing by performing
process and proximity correction concurrently. This unique technology
delivers superior results with 6X to 10X productivity improvement. Come
witness how it can deliver revolutionary results in your fab.
Improving Time to Volume Manufacturing by Design Including Double Patterning
As consumer products increasingly drive the semiconductor industry, time to volume
manufacturing is critical in the success of a product. Witness the benefits of
preventing, analyzing, and optimizing manufacturability variations in the design
space to ensure that your design is correct by construction. Find out about a more
streamlined flow to implement double patterning techniques.
Intelligent and optimized flow for yield ramp
Cadence® Encounter® Diagnostics is a complete, intuitive, full-function solution
for ramping yield on high-volume devices. Its highly accurate simulation engine,
robust volume analysis environment, and physical layout browsing capability will
be shown quickly analyzing hundreds of failures to identify the source of systematic
yield loss. Links to Design for Manufacturability tools will be presented to
accurately pinpoint specific defect locations in the netlist and layout.
Manufacturing-aware implementation for advanced node design
With the advent of 45nm semiconductor technology, systematic variations due to
lithography and CMP must be taken into account during SoC, ASIC and custom
designs to avoid large margins applied at every stage of the design, long
timing closure cycle time, poor yield and costly silicon respin. This demo
shows how to ensure "what-you-design-is-what-you-get" on silicon — and how
designers can deploy the comprehensive Cadence manufacturing-aware design
methodology to prevent variations due to litho and CMP—which can create
catastrophic or parametric failures—using prevention during routing, detect
them using foundry-certified model-based solutions, automatically repair them,
and analyze their parametric impact using Cadence advanced parasitic extraction.
Where and When
Moscone Center
747 Howard Street
San Francisco, CA 94103
415.974.4000
Tuesday, July 15, 2008, 10:00am - 6:00pm
Wednesday, July 16, 10:00am - 6:00pm
Thursday, July 17, 10:00am - 4:00pm
Questions about this event?
Send email to events@cadence.com Register
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