Cadence Design Systems, Inc.

In the News

July

07/08/08	ESL Handoff: Closer Than You Think - EDA DesignLine

June

06/16/08	Russia moving on fabless development path, says Cadence - EE Times Europe

06/16/08	EDA healthy and growing in India - CIOL

06/12/08	Mobile growth: 'Exponential curve' or Dead Man's Curve? - EE Times

06/12/08	Prestigious Panel Recognizes Important Industry Innovations at SEMICON West - Nanowerk

06/12/08	2007 International Test Conference papers - IEEE

06/10/08	Cadence, Synopsys Team with ARM for 45-nm Low Power Common Platform Flow - Electronic News

06/10/08	Reference Design Targets UMC 65nm Process - Electronics Talk

06/10/08	Verification IP Products Suit OVM Users - Electronics Talk

06/06/08	European User Conference Addresses Design Automation Challenges - Components in Electronics

May

05/20/08	May Institute gets $1M from California company - Boston Business Journal

05/18/08	49ers Take Part in Stars and Strikes - 49ers.com

05/15/08	Unified EDA Flow for Analog Designs and PCB Implementation - SMT

05/06/08	How floorplanning guides synthesis and physical design - SCD Source

05/06/08	DRC signoff doesn't cut it for next-gen nodes - EE Times

05/01/08	Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform - EDN

April

04/29/08	Cadence offers new custom IC design capabilities - SCD Source

04/29/08	Cadence Debuts RTL to GDSII Reference Flows for ARM Cortex-A9 - EDA Geek

04/28/08	New standards effort targets verification IP interoperability - SCD Source

04/28/08	Q&A: Cadence's Vucurevich On Processing Power's Continued Importance - Gamasutra

04/28/08	Accommodating Change - IC Journal

04/22/08	What floorplan information is needed for synthesis - EDA DesignLine

04/22/08	Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems - Chip Design Magazine

04/17/08	Cadence Announces Reentry Into Upstream Design in Japan - Tech-On!

04/17/08	Validating false path timing exceptions - SCD Source

04/15/08	It's time to shift the low power debate - SCD Source

04/12/08	Multi-language Functional Verification Coverage for Multi-site Projects - EDA DesignLine

04/04/08	Viewpoint: Verification flow should be front and center - EE Times

04/01/08	Open Verification Methodology: Why Now? - EDA DesignLine

04/01/08	'Openness' fulfills SystemVerilog promise - EE Times Asia

March

03/31/08	On-Chip Thermal Analysis Is Becoming Mandatory - Chip Design Magazine

03/31/08	Tool Automates Engineering-Change-Order Generation - Electronic Design

03/25/08	Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems - Chip Design Magazine

03/21/08	Power Forward group launches low-power design methodology guide - EDN

03/19/08	The Perils of 45nm: A Report on the Move - IET TV

03/18/08	How to specify and verify power-cycled SoCs for checking and coverage - Electronic Business

03/10/08	Practical Case Study In Low-Power Design Methodology - EPN Online

03/06/08	Is it really a black art or just a red herring? - DAC e-Zine

03/05/08	If you can't measure progress against your plan, you have no plan! - Chip Design Magazine

03/05/08	Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM - Solid State Technology

February

02/27/08	Power mode technologies verify today's SoCs - EE Times

02/26/08	Improving design turn around time on a complex SoC by leveraging a reusable low power specification - Design & Reuse

02/25/08	Formal verification expands its use model - SCD Source

02/22/08	Pizarro: Bowling benefit to aid autistic children - San Jose Mercury News

02/21/08	The Brewing Standards War - Verification Methodology - Cool Verification

02/18/08	Multi-language Functional Verification Coverage for Multi-site Projects - EDA DesignLine

02/13/08	Where's the ROI in DFM? - EDN

02/11/08	SPIE and the IC design world: a wall starts coming down - EDN

02/06/08	Open Verification Methodology offers interoperability - SCD Source

02/05/08	IEC Today Announces Winners of Highly-Coveted DesignVision Awards at DesignCon 2008 - International Engineering Consortium

January

01/29/08	A Methodology to Speed DFT Signoff - Evaluation Engineering

01/23/08	Cadence Encounter RTL Compiler wins synthesis poll - EE Times

01/21/08	Automated Formal Verification of OCP based IP Cores - EDA DesignLine

01/16/08	Coverage-driven verification for mixed-signal systems - SCD Source

01/14/08	Commentary: 'Open' is (not) just a four-letter word - EE Times

01/09/08	"Let the mayhem begin!": Open Verification Methodology available for free download - EDN

01/09/08	Cadence, Mentor roll verification tool - EE Times

01/09/08	Open Verification Methodology ready for download from Cadence, Mentor - EDN

01/04/08	Physical predictability for carbon-neutral timing closure - EE Times

01/02/08	Ten 2008 Trends in System and Chip Design - SCD Source

01/01/08	Executive Outlook: Driving Productivity, CoO in 2008 - Semiconductor International