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Open Verification Methodology from Cadence and Mentor Now Available for Free Download
Access the Award-Winning Interoperable SystemVerilog Methodology on the New OVM Website
The Open Verification Methodology (OVM)—the industry's first open,
interoperable SystemVerilog verification methodology—was recently honored
with a "2007 BEST" award for EDA technology from Electronic Design Magazine,
and named a finalist for a DesignVision award from the International Engineering
Consortium (IEC). Now users can access this award-winning technology by downloading
the OVM source code, documentation, and use examples free of charge from the
OVM website.
The website also offers information about partners, events, seminars, training,
how-to instructions, and future plans for OVM.
Based on Std. 1800™-2005 SystemVerilog standard, OVM provides a library
of classes that allow users to create modular, reusable verification environments
in which components communicate with each other via standard transaction-level
modeling interfaces. It also enables intra- and inter-company reuse through a
common methodology and classes for virtual sequences and block-to-system reuse,
and through full integration with e and SystemC. Cadence and Mentor Graphics
jointly developed OVM as an open source verification solution for the whole
industry. This collaboration ensures that the methodology runs on Cadence and
Mentor simulators and enables backwards compatibility with both companies'
existing environments, including the Advanced Verification Methodology from
Mentor, and the Cadence® Incisive® Plan-to-Closure Methodology
(Universal Reuse Methodology module).
OVM includes the foundation-level utilities necessary for building
advanced object-oriented, coverage-driven verification environments
and reusable Verification IP (VIP) in SystemVerilog. It reduces the
complexity of adopting SystemVerilog by embedding verification practices
into its methodology and library, and significantly shortens the time to
create verification environments through easy integration of plug-and-play
VIP and by ensuring code portability and reuse.
Making the OVM source code available to the whole industry is the first
step in delivering on the full promise of SystemVerilog.
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