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Cadence Integrates SiP Technologies Into Latest Custom and Digital Design Flows Manufacturers of high-performance consumer electronics are turning to SiP design because it can provide a number of advantages over SoC. In addition to reduced cost, lower power, and higher performance, SiP design offers the flexibility to mix RF and high-speed digital circuitry in the same package. However, this also means that SiP design requires expert engineering talent in widely divergent fields. Continuing to build on its leadership in SiP design technology, Cadence now delivers significant new design capabilities and productivity enhancements to system-level IC and package design. These improvements, combined coupled with already available Cadence® RF SiP Methodology Kit and other products further enables companies to mainstream what was an expert engineering design process.  |  | | | | "As a user of both Virtuoso and SiP it's important to have the best integrated overall solution and flow. The latest SiP 16.0 technology delivers new levels of integration and design productivity that we need in order for us to deliver leading edge multi-chip package solutions to our customers." | | | | Christian Caillon, | | | Engineering Director, Cellular Communication Division | | | STMicroelectronics | | | | | |
Cadence SiP technology is now integrated with the new OpenAccess-based Virtuoso® customer design platform (release IC 6.1.1) for an RF module design and circuit simulation-based flow. For the SiP digital flow, this release includes logical co-design connectivity authoring support and enhanced integration with Cadence SoC Encounter™ RTL-to-GDSII system for enhanced I/O planning with staggered bondpad and radial wirebond bondpad spacing support. Other significant features in the latest release of SiP technology include:  | Autobond for rapid wirebond padring evaluation | | Object-action and action-object use models | | Improved SI model extraction accuracy for designs without reference planes | | 3D die stack object swapping | | Extended manufacturing signoff rules | | Capabilities for manufacturing accurate wirebond profiles and parasitic models |
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