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PowerPC Design Services To streamline the process of embedding PowerPC 4XX cores in SoCs, Cadence® offers a comprehensive set of consulting services, including a new custom-synthesized design approach that delivers up to a 30 percent increase in processor speed and a 40 percent reduction in chip area. Cadence has developed these silicon-proven services specifically for customers that need to embed PowerPC 440, 405 and future 4XX cores into SOCs with the fastest performance and smallest area requirements. Cadence has successfully implemented the PowerPC 440 core in 130nm silicon, and used the Cadence Palladium® accelerator/emulator to perform emulation for the software co-design. By enabling RTL verification and software validation at speeds of 500 kHz to 1.2 MHz—versus 25 Hz to 50 Hz for simulation—Palladium provides the ideal platform for the development of multi-core and multi-processor SoCs based on the IBM Power Architecture. In addition, Cadence has developed a flow—using RTL Compiler, Test Encounter and SoC Encounter—that is tuned for the PowerPC. New custom-synthesized design approach
Developed in close collaboration with IBM, the Cadence custom-synthesized approach provides a new schedule/performance tradeoff point for performance-minded SoC designers embedding PowerPC cores. It advances PowerPC portability in markets such as consumer electronics and networking, where a full-synthesis approach may not yield the desired processor speed and area, but where time-to-market constraints prohibit employing a full-custom approach.
Cadence Engineering Services helps customers achieve these results using the Cadence Virtuoso® custom design platform to do full-custom design on the eight to 10 design blocks that have the greatest influence on timing, power and area, such as the demanding CAMRAMs on the PowerPC 440 core. The remaining blocks are designed using Cadence RTL Compiler synthesis, which delivers market-leading results for cycle time and chip real estate in PowerPC applications. This approach has been verified in a silicon test chip that contains the PowerPC 440 core targeted to the TSMC 130nm LV process. This test chip not only includes the PowerPC 440 core but also implements the PLB4 bus, a bridge to the AMBA2.0 bus, and various pieces of IP associated with each bus. This silicon device is designed to work at 333 MHz in a worst-case scenario of process, voltage and temperature conditions. Testing and characterizing activities have shown that parts of this silicon work at 480 MHz and faster. PowerPC projects currently underway include the 440 core implemented in 90 and 65nm processes, with initial customer discussions underway for implementing the same core targeted at 45nm. An extension of your team
Cadence Engineering Services can assist in your project with consulting services that include:
 | Porting and integration of PowerPC macros in processor-based SOCs | | Palladium hardware emulation and RTL model development | | Support for various cache configurations (i.e., 16K I-cache, 1-way D-cache, no cache) |
Cadence Engineering Services works collaboratively with your design team and can accommodate any level of interaction and knowledge transfer that your business needs dictate.
| Cadence SoC platform for the PowerPC 440 |
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