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PRODUCTS
SoC Encounter
First Encounter
Encounter RTL Compiler
Encounter Test
Encounter Conformal ECO Designer
Encounter Conformal Equivalence Checker
Encounter Conformal Constraint Designer
Encounter Conformal Low Power
Encounter Timing System
Encounter Library Characterizer
CeltIC NDC
NanoRoute
VoltageStorm
Cadence QRC Extraction
Cadence Chip Optimizer
Cadence SiP Digital Architect
Cadence SiP Digital Layout
Cadence SiP Digital SI
DESIGN TASKS
High-performance timing closure
Implementation of large-scale designs
Analysis and signoff
Design for Manufacturing
Mixed-signal design
Applications Using the ARM Cortex-A8 Processor
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
IP catalog
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Cadence Nanometer Test Quarterly eNewsletter

The Nanometer Test Quarterly eNewsletter is published by the Cadence® Encounter® Test team to keep you informed about important technology updates, issues, and solutions in nanometer test.
  • Technology updates
  • Product updates
  • Customer success stories
  • Articles
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Current issue



Volume 2, Issue 3 - August 2005 
In this issue read about topics such as yield-enhancement architecture from the semiconductor industry, delay-test primer, a method for simplifying delay testing, and modeling and testing bridging defects in Encounter Test.

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