 | | Dan Dobberpuhl
President and CEO, P.A. Semi
Dan Dobberpuhl talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
 | | |
 | | Amit Chandra
Sr. Engineering Manager, P.A. Semi
Amit Chandra talks about using the Encounter platform to overcome high-performance, low power design challenges.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Chris Silsby
Agilent Technologies
The Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Eric Broockman
Alereon, Inc. CEO
Cadence and Alereon partner to design the world's highest performance ultrawideband chipset.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Paul Holt
Vice President, Product Development and Services
Paul Holt, Vice President, Product Development and Services, ARC International, discusses how Cadence and ARC optimize flows for configurable processors and multimedia subsystems, reducing customers? risk and enabling them to get to market quicker.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Doug Shute
Bitwave Semiconductor CEO
Bitwave and Cadence combine to develop software-defined radio.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Bret Zahn
Vice President, Design and Characterization, ChipPAC
Cadence IC Packaging solutions help ChipPAC increase communication and easily pass designs between designers around the world.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Paul Nahi
Crimson Microsystems President and CEO
Crimson and Cadence work together to create the worlds most advanced MSPP-on-a-chip.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Toby Farrand
Chief Technical Officer, Digeo
Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Jochen Reisinger
Engineering Director SiP
Cadence and Infineon Technologies collaborate to bring system-in-package design to mainstream.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Bill Carlson
Intel
Cadence Allegro PCB SI (SPECCTRAQuest) helps Intel significantly reduce overall development time for evaluation boards.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Greg North
Chief Technology Officer and VP of Engineering, Luminary Micro
Greg North talks about using the Encounter platform to overcome nanometer design challenges.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Tim Richardson
Micro Linear CEO
Micro Linear and Cadence collaborate on successful next-generation RF transceiver design.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Martin Spohr
Senior Engineer, NEC Electronics
Martin Spohr talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Vincent Mouret
NemeriX
Cadence and NemeriX team up to produce industry leading GPS Chipset
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Bruce Cory
DFT Methodology Manager, nVidia
Bruce Cory talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Chris Malachowsky
nVidia
nVidia VP of Engineering Chris Malachowsky talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help nVidia get results.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Patrick Scheer
Philips
The Palladium™ accelerator/emulator helps Philips Semiconductors speed up their verification by 57X.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | John Glossner
Sandbridge Technologies CTO
Sandbridge and Cadence set out to revolutionize mobile handsets with a multi-threaded DSP architecture.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Dave Shepard
Sequoia Communications President & CEO
Sequoia and Cadence develop revolutionary new RF transceiver architecture.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Martin Goldberg
CAE & Board Design Director, Siemens
Siemens looks to Allegro PCB SI (SPECCTRAQuest signal integrity expert suite) for added simulation functionality, eliminating PCB signal integrity challenges.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Steve Stern
Sipex
Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Laurent Mailet-Contoz
Project Leader, STMicroelectronics
ST uses Incisive verification platform at the transaction level to reduce their design cycle and help the company to be the first to new markets.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Jai Kumar
Verification Technologist from Sun Microsystems
Jai Kumar, Verification Technologist from Sun Microsystems shared his verification experience of advanced development of UltraSPARC processors with Cadence Incisive Xtreme series.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Uday Kapoor
Director of Corporate CAD, Sun Microsystems
The Allegro PCB SI (SPECCTRAQuest signal integrity expert suite) helps Sun Microsystems eliminate noise in high-speed power delivery systems for PCBs.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Tim Jaynes
Applications Engineer, Xilinx
Cadence helps Xilinx develop a silicon design-in kit with Allegro PCB SI (SPECCTRAQuest) to shorten their customers time to design-in RocketIO transceivers.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Edwin Li, Ph.D.
Zeevo
Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Bob Bridge
Zilker Labs CEO
Zilker Labs and Cadence merge power management and power conversion into the ZL 2005 IC.
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
| | |
 | | Thilo von Selchow
ZMD CEO
ZMD and Cadence Engineering Services work together to produce cutting edge ZigBee wireless solution
REAL MEDIA:Low(35K) | Med(100K) | High(250K) |
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