Cadence Design Systems, Inc.

Partners Articles

12/18/07 Addressing low-power issues in chip design
10/24/07 CPF-Based, Low-Power Digital Reference Flow
04/06/07 Women of Distinction Awards Pay Tribute to Some of Silicon Valley's Most Powerful and Inspiring Women
04/06/07 Winner: Jan Willis
01/12/07 Si2 approves low-power spec, seeks 'convergence'
11/05/06 Pushing Power Forward with a Common Power Format
09/05/06 Cadence moves to broaden power initiative
05/25/06 TSMC, UMC Ready for 65-nm X Architecture Designs
05/22/06 Initiative Seeks Common IC Power Format
05/22/06 Cadence Led Initiative Seeks Low Power Standard
05/22/06 Standard Format to Automate Low Power IC Design
03/24/06 Fueling Innovation with Vertical Re-aggregation
03/07/06 Si2 Releases Current-source Model Standard for Design Libraries
02/28/06 Silicon Design Chain - Second Power Management Methodology
02/08/06 Innovators of Electronic Design Honored
01/19/06 Global Designer: IEEE Standardizes SystemVerilog
01/12/06 Cadence Claims X Architecture Boosts Net Good Die Per Wafer by a Minimum of 10%
12/05/05 Open-source Database Links Today's Hodgepodge of Tools
12/01/05 Virtual vs Vertical - How will DFM Change the Foundries?
11/11/05 OpenAccess Simplifies Chip Makers' Lives
11/11/05 Freescale, Cadence Said to be Seeking Deal to Cut EDA Costs
11/07/05 OpenAccess Effort Has Momentum
11/04/05 Panelists Optimistic on Lower Power Design
11/04/05 Panelists Ponder Challenges of 45nm
11/04/05 Panel Studies Power on SoCs
10/06/05 Cadence, UMC Develop Reference Design for Wireless
09/22/05 Collaboration and the X Factor
09/09/05 Who Sets the Design Rules?
09/08/05 Cadence supporting OpenAccess 2.2
09/05/05 OpenAccess: first impressions at AMD
09/01/05 Case Study: Collaboration Success for Fabless Wireless IC Start-up in China Market
08/29/05 Designing ICs with the 'X' Architecture
08/18/05 Get Up Close and Personal with Silicon Foundries
07/27/05 Cadence, Accent, ARM Improve Low-power Design
07/25/05 Multi-voltage Cuts Chip Power by 40%
07/18/05 Leaky Chips Test Designers' Skills
06/20/05 The search for semiconductor IP intensifies
06/16/05 Power Puts Moore's Law in Danger
06/16/05 Search for Low Power Continues at DAC
06/15/05 Open Modeling Coalition launches at DAC
06/13/05 ATI, TSMC, Cadence Move X Architecture Closer to Production
06/13/05 Cadence 45ø X-Architecture Gets Cheers from ATI
06/13/05 ATI Produces First X Architecture Chip, Says Cadence
06/13/05 ATI positive on diagonal routing
06/09/05 TSMC releases reference design flow for 65-nm processes
06/08/05 Rebuilding Momentum in EDA
04/14/05 Low-power Design Techniques Drop 90nm Consumption
04/11/05 UMC poised to use X architecture for 90-nm chips
03/01/05 Collaborative DFM Critical for Enabling Nanometer Design
02/14/05 Designing for Yield Heats Up
02/14/05 IEEE SystemVerilog Heads Towards Balloting
02/03/05 Experts debate how to leverage design-for-yield
02/03/05 Special Market Focus: Collaborative Design, Part Two
01/27/05 Special Market Focus: Collaborative Design
01/17/05 Open-source Project Looks to Ignite EDA Research
01/01/05 Dot.Org-Si2: Innovation Through Collaboration
11/29/04 SystemC Presses IEEE Standardization
11/19/04 Focus On Results in System Language Debate
10/11/04 Methodology Sought For Assertion-based Verification
09/30/04 Accellera Re-elects Officers, Cites Progress in IEEE
06/15/04 Cadence Promises Full SystemVerilog Support
06/14/04 X routing heads for fab
06/09/04 Can You Build It?
06/08/04 Cadence adds DFM tools to Encounter
06/07/04 EDA at a Crossroads over Verilog's Future
06/01/04 Accellera reneges on IEEE SystemVerilog transfer
05/27/04 Verilog schism feared as Accellera bypasses IEEE 1364
05/14/04 EDA vendor, Accellera moves place SystemVerilog at crossroads
02/03/04 OpenAccess users cite successes, concerns
01/19/04 OpenAccess claims inroads among design EEs
01/19/04 CoWare forges a SystemC link for its SPW tool
01/01/04 Time Travel to 2029: Nanotechnology Thrives
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