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Provision of a New CPF-Adopted Low-Power Consumption Design Flow
NEC Electronics has achieved a simulation environment which supports the
CPF (Common Power Format) to facilitate verification at the architecture
design stage. A design to achieve optimal low-power consumption can be
performed through logic simulation, including multi-power supply systems
as well as power control, by adding ideas for lowering power consumption,
which are described in the CPF, to the RTL module in which design information
is described. With our short-turnaround time, high-quality, and established ASIC design flow,
sophisticated low-power consumption architecture can be easily developed into an
LSI (Large Scale Integrated Circuit) and provided to customers by expanding to
the CPF design flow our state-of-the-art power reduction technology obtained
through the ASSP development of mobile LSIs or the like.
| CPF-Adopted Low-Power Consumption Design Flow |
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The common power format plays an important role in communicating the power
information throughout the entire design flow from simulation through implementation.
Based on our extensive track record and experience in low-power consumption
design, we have participated in the standardization establishment activities
of the Power Forward Initiative (PFI) from the early stages, and have
contributed to the practical application of CPF. We are currently preparing
for the introduction of the standard format [Common Power Format (CPF)] by
Silicon Integration Initiative (Si2), Inc., as the common power format.
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