CADENCE AND IBM ASIC PARTNERSHIP
IBM has always been known as a technology leader; and with nearly 30 years of experience designing and manufacturing ASIC products behind that leadership. IBM's proven methodology, tools and services allow them to implement state-of-the-art technologies in an efficient and streamlined way, making them the leading ASIC logic supplier in the world.
IBM's integrated design flow takes an ASIC design from start to finish—from design entry and planning, when a design is little more than an idea; to the silicon implementation of the design produced on their manufacturing lines; to the complete packaged-silicon solution. This design flow allows an ASIC customer to take advantage of industry-standard tools along with IBM's leading-edge tools and models, all seamlessly woven together.
Cadence® has a deep-rooted relationship with IBM. Cadence is an Advanced IBM Business Partner and has collaborated with IBM to support IBM ASIC methodology and technologies with Cadence EDA tools and solutions. The following IBM ASIC methodology tool matrix shows the areas where Cadence technology is being applied to meet the technical demands of IBM's ASIC customers in their ASIC methodology.
IBM ASIC Technology and Cadence Product Matrix
| Library |
CU65 |
CU08 |
CU11 |
SA-27 |
SA27E |
| Updated |
2006- 01-15 |
2005- 01-15 |
2005- 01-15 |
2005- 01-15 |
2005- 01-15 |
| Process |
0.065 |
0.090 |
0.130 |
0.150 |
0.150 |
| Technology |
CMOS |
CMOS |
CMOS |
CMOS |
CMOS |
| Cell Type |
Standard Cell |
Standard Cell |
Standard Cell |
Standard Cell |
Standard Cell |
| Voltage |
1.0V |
1.0V |
1.5V |
1.8V |
1.8V |
|
| IBM ASIC methodology task |
Cadence Qualified Tool |
| Behavioral Simulation |
Cadence NC-SIM |
| Top-Level Insertion |
IO Spec DFT |
| Logic Synthesis |
Encounter RTL Compiler |
| Physical Synthesis |
Encounter GPS |
| Design Planning |
First Encounter |
| Test Synthesis |
Encounter Test Architect |
| Test Structure Verification |
Encounter Test Design Edition |
| Formal Verification |
Conformal LEC |
| Gate Level Simulation |
NC-Sim, Palladium Hardware Acceleration |
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