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ASIC Partner Program


As designs grow more complex at lower technology nodes, ASIC suppliers need technologies that produce smaller, faster and cooler chips in less time in order to increase their competitiveness and reduce overall costs. Cadence® collaborates with its ASIC partners to ensure that engineers using Cadence technology and platforms are provided with an optimized solution for the ASIC partners flow and design kits.

A key area of collaboration is improving RTL handoff to ASIC customers through world-class synthesis technology. Cadence Encounter® RTL Compiler has been proven through tape-outs to improve performance, shrink die sizes, lower power consumption, and speed design closure via place and route.

As part of the ASIC Partner Program, partners not only benefit from innovative technology and comprehensive support services but also enjoy access to customized training and joint marketing promotions, enabling them to highlight the value of collaborative solution to their target customer base.

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What's new

Renesas / Cadence ASIC Announcement
Adopts RTL Compiler for 90nm and below designs

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