CADENCE AND SAMSUNG PARTNERSHIP
SAMSUNG's vision for its logic foundry is to serve both fabless
and IDM semiconductor companies creating leading-edge products on
300mm wafers. Targeting the high-end segment of the market, Samsung
Foundry offers process technology solutions at 90nm, 65nm, and now
45nm through its collaboration with the Common Platform Technology
Alliance. Our dedicated logic foundry, named the S-1 line, is located
in the heart of our System-LSI campus in Giheung, South Korea.
Samsung develops, distributes and supports PDKs based on the Cadence
Virtuoso custom IC design platform. These PDKs are tuned to Common
Platform Digital-CMOS processes at 90/65/45nm and can improve design
start-up time, boost designer productivity, and improve design quality.
Samsung-supplied PDKs include device models for Spectre/HSpice, PCells,
Symbols, Virtuoso XL tech files as well as LVS/RCx rule decks for Assura.
PDKs are available by contacting your Samsung account manager
Cadence, IBM, Chartered and Samsung have developed RTL-to-GDSII Reference
Flows based on the Cadence Encounter Platform and targeted to the Common
Platform 90nm and 65nm CMOS processes. These jointly developed reference
flows use a wire-centric methodology to address key SoC design issues
including low power, signal integrity, and design for manufacturability
to provide the highest quality of silicon (QoS).
The 65 nm low power reference flow kit for the Common Platform can be
accessed here. This reference flow kit contains a reference design,
documentation and scripts to run the reference flow. Additional information
on the reference flow can be found in the datasheet.
The following PDKs are currently available from Samsung:
 | BiCMOS BS3550 | | CMOS/RF LR18 | | Mixed Signal/RF L13GMSRF | | CMOS L9G | | CMOS L9LP | | CMOS/RF LR9LP | | CMOS L6LP | | CMOS/RF LR6LP | | CMOS L4LP |
|
|
 |
|
|
