SystemVerilog
SystemVerilog is an evolving solution and candidate IEEE standard (P1800)
that expands on base VerilogŪ language by adding convenience and abstraction
extensions for design. It is then further extended with assertions and
multiple levels of testbench constructs for verification. SystemVerilog
is well suited for designers wishing to take on or contribute more to RTL
verification tasks with limited complexity. Most vendors are in the
process of coupling an incrementally larger subset to methodology, technology,
and verification IP (VIP).
The Open Verification Methodology (OVM)
is the first truly open, interoperable, and proven verification methodology.
The OVM is an open-source SystemVerilog class library and methodology that
defines a framework for reusable verification IP (VIP) and tests. It is 100%
IEEE 1800 SystemVerilog and provides building blocks (objects) and a common
set of verification-related utilities. The OVM release will be under the
Apache 2.0 license, enabling anyone to use OVM libraries for any purpose,
including creation of derivative work. The OVM is jointly developed by
Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability
with a standard library and a proven methodology.
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