VHDL


		VHDL


		SystemVerilog


		Property Specification Language (PSL)


		SystemC


		e Verification Language


		ECSM library format


		Open Verification Methodology

VHDL

VHDL (IEEE 1076-2000) enjoys a similar position to Verilog in several geographic and industry segments. While its precise semantics and higher level abstraction appeal to some, it has never fully realized its potential largely because of the lack of gate-level support. VHDL will remain the language of choice for many designers due to its capabilities and legacy.





	Introducing the Open Verification Methodology (OVM) SystemVerilog Cadence and Mentor standardize on a tool-independent solution promoting data portability and interoperability. OVM Recognized by Electronic Design magazine SystemVerilog methodology named a Best EDA Technology for 2007.



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