ARC International
ARC International is a leader in configurable subsystems and CPU/DSP processors used by semiconductor companies worldwide for leading-edge SoC design. ARC's patented configurable processor technology enables the development of consumer, networking, and other cost-sensitive devices that are smaller, more differentiated, and consume less power than what can be created using "fixed architecture" alternatives.
Encounter platform optimized for ARChitect processor configurator
Capacitance, inductance, resistance, and crosstalk conspire at sub-100nm process geometries to thwart a design team's efforts to produce right-first-time silicon that meets critical timing and power requirements. To address this industry-wide challenge, Cadence and ARC have optimized integration of the Cadence® Encounter® digital IC design platform with ARC's patented ARChitect processor configurator. ARC licensees now can produce RTL, synthesis, and floorplanning scripts that are tuned to the Encounter Reference Methodology. This helps SoC designers better anticipate the behavior of electrical signals and ensure the design is fully verified before going to silicon. ARC joined the Power Forward Initiative in 2006, deepening their commitment to solving low-power design challenges.
The Encounter platform provides a proven path to silicon for the ARC 600 and ARC 700 configurable core families by characterizing and accommodating all the circuit effects that proliferate in the interconnect layers of nanometer processes. The ARChitect processor configurator handles the noncreative part of the design flow, freeing designers to use the tool creatively to add or remove ARC core components, which increases functionality and differentiates their SoC designs.
ARChitect processor configurator
The ARChitect processor configurator enables SoC designers to rapidly create customized ARC processor core designs optimized for specific applications—without increasing project complexity or risk. Using the ARChitect tool's drag-and-drop GUI, designers can add or remove features to and from their applications. Configuration options include features around the core (such as type and size of caches, interrupts, DSP subsystems, timers, and debug components) as well as features within the core (such as type and size of core registers, address bus widths, and instruction set options). Designers can quickly optimize tradeoffs between performance and die size. The resulting cores invariably will be smaller and consume less power than "fixed architecture" cores.
Encounter Reference Methodology
Integrated with the ARChitect tool, the Encounter Reference Methodology allows designers to quickly develop a detailed, full-chip silicon virtual prototype including characterized routed wires. Integral to the platform methodology is a flexible GUI, a customized flow, the ARC 600 or ARC 700 configurable core family reference designs, and a base technology/library infrastructure. The methodology provides completely validated synthesis and floorplanning scripts, allowing SoC designers to implement the latest technology quickly with minimal ramp-up.
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