CADENCE AND ARM PARTNERSHIP
ARM is the industry's leading provider of 32/16-bit embedded RISC microprocessor solutions. Cadence and ARM collaborate closely to ensure that ARM intellectual property (IP) and Cadence design and verification solutions are optimized for the successful design of ARM core-based SoCs. The two companies recently entered into a new 5-year agreement targeted for mutual customer's success. This collaboration will enable customers to build systems with verified, reusable hardware and software IP blocks faster and with greater confidence that the systems will be manufacturable the first time.
Designing with embedded processors, such as the ARM® Cortex™-A8 processor, for low-power mobile and consumer applications presents a number of challenges including shrinking geometries and power efficiency. It also requires large numbers of designers and months of design time.
CADENCE OPTIMIZATION METHODOLOGY KIT FOR ARM PROCESSORS
The Cadence® Optimization Methodology Kit for ARM Processors massively simplifies the implementation techniques used to achieve higher performance, lower power and less area (PPA) for ARM-based designs. The kit couples expert service and support with industry-leading Cadence Encounter RTL Compiler global synthesis, First Encounter virtual prototyping and ARM's Artisan TSMC 0.13m SageX and TSMC 90G libraries. With this package, customers can achieve specified PPA levels and substantial reductions in development time required for hardening ARM processor cores. The Cadence Optimization Methodology Kit for ARM Processors has been designed to provide significant low power optimization enhancements to the ARM-Cadence Encounter Reference Methodology  .
Click here for more information on the ARM Implementation Reference Methodology (iRMs).
CADENCE FUNCTIONAL VERIFICATION KIT FOR ARM
Jointly developed by Cadence and ARM, the Cadence® Functional Verification Kit for ARM offers a comprehensive verification solution specifically for engineers developing ARM® processor-based designs. The Kit contains ARM processor-based verification methodology and flows, a reference design platform, verification process automation (VPA) technology, and reusable verification IP. The proven Incisive® Plan-to-Closure Methodology from Cadence has been tailored specifically to ARM processor-based designs. Download PDF overview document .
ARM-CADENCE ENCOUNTER REFERENCE METHODOLOGY
The ARM-Cadence Encounter Reference Methodology is a key deliverable of an ongoing collaboration between the two companies.
The Reference Methodology provides a wire-centric, integrated implementation flow from RTL-to-GDSII that delivers predictable performance, power and area results for ARM soft core licensees. This signal-integrity enabled flow speeds time-to-volume by ensuring that the on-chip noise and IR drop effects seen at sub 180 nm technologies are accounted for. Additionally, the flow incorporates Encounter RTL Compiler, a new generation synthesis solution that provides improved Quality-of-Silicon (QoS) results compared to other commercially available solutions.
SILICON ENGINEERING
ARM licensees can benefit from the extensive experience that Cadence has in delivering nearly 40 successful tape-outs of ARM Powered designs. Cadence Silicon Engineering provides customers with superior silicon through optimizing the physical implementation of silicon to match the architecture of their SoC designs. Cadence design centers have been approved by ARM for customers who choose to outsource all or part of their design activities. The Cadence Livingston, Scotland Design Center was the first member of ATAP, the ARM technology access program.
CADENCE INCISIVE VERIFICATION PLATFORM
Cadence collaborates with ARM on SystemC®-based transaction-level interfaces and methodology so customers developing ARM core-based SoC designs can visualize and validate the full system early in the design process. Components of the solution leverage the Cadence Incisive verification platform combined with ARM's integrator logic tile product for high-speed unified verification. This next-generation SoC solution based on the AMBA bus standard will dramatically decrease the time, effort, and risk required to design and verify complex SoCs.
SoC POWER GRID VERIFICATION
ARM and Cadence have worked in partnership to develop pre-validated power grid libraries for ARM Foundry Program licensees that are users of Cadence's VoltageStorm power grid verification software.
At 0.18-micron and below, interconnect effects require designers to analyze the impact of IR drop on the performance and functionality of their chips. VoltageStorm enables designers to verify the integrity of their power grid before signal routing.
Power grid views libraries for signal integrity sign off of designs incorporating ARM processors are available by request from ARM.
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