CADENCE AND DENALI ALLIANCE
Denali Software, Inc. is a world-leading provider of electronic design
automation (EDA) software and intellectual property (IP) for
system-on-chip (SoC) design and verification. Denali has collaborated
with Cadence to create a DDR PHY hardening methodology using the
Cadence® Encounter® digital IC design platform to reduce
implementation time.
The DFI compliant Denali Hard PHY IP block is a complete
GDSII solution ready to be integrated into SoCs and ASICs
which interface with DDR memories.
Each PHY is delivered to match the unique requirements of
the customer's DDR
application. Using Denali's Hard PHY reduces risk and
time-to-market for deploying memory interfaces in silicon.
The PHY is configurable for data width, ECC, low power, and many other
options. DDR1/2/3 and LP-DDR1/2 devices are also supported.
PHY design typically takes months with significant effort for timing closure,
particularly at the high DDR memory interface speeds common today. Denali
has created a methodology using
the Cadence Encounter digital IC design platform
to reduce implementation time to weeks, including timing closure and DFM.
Denali recommends the use of Cadence SoC Encounter™
and Encounter Timing System for the DDR PHY. SoC
Encounter enables designers to intelligently place the macros
within the PHY (such as the DLL and match cells). Clock tree
synthesis and detailed routing are then performed with signal
integrity (SI) effects taken into account. All steps in the physical
implementation flow within SoC Encounter are automatically
driven by the identical electrical signoff quality analysis engines
within the Encounter Timing System. This consistent view
of timing through the flow ensures minimal iterations between
implementation and signoff to reach final design closure.
The "PHY compiler" methodology using Cadence Encounter
platform ensures last minute changes will not adversely affect
delivery schedules.
More information
PCI Express
Denali and Cadence have also collaborated on a best-in-class flow
for verifying PCI Express designs. The flow is centered around
Denali PureSpec verification within the Cadence Incisive Verification
Platform. PureSpec is a verification IP product used in Incisive to
simulate, and verify PCI Express design interfaces. PureSpec models
all devices in the PCI Express topology, including the root complex,
switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all
protocol layers (physical, data link, transaction) of the PCI Express
specification are completely modeled and can be simulated concurrently
or independently. The product contains thousands of assertions that
are monitored during simulation to ensure compliance with the PCI Express
specification, and interoperability with other PCI Express devices.
The PureSpec verification IP has been used on over 40 PCI Express
designs, making it the most widely used and trusted source for verifying
compliance and interoperability for PCI Express interfaces.
The PureSpec PCI Express verification IP is integrated and proven for the following Cadence products:
 | NC-Verilog via PLI | | NC-VHDL via VHPI | | NC-SC via Denali Yukon API | | SpecMan Elite | | Simulation Analysis Environment (SimVision) via database export |
Denali Databahn Memory Controllers and Encounter® RTL Compiler
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Denali also supports Cadence Encounter RTL Compiler global synthesis
on Databahn memory controller products. Encounter RTL Compiler synthesis
enables Denali customers to achieve smaller, faster and lower power
implementations for Databahn DRAM controller designs. Denali used a
top-down methodology featuring its market-leading Databahn memory controller
IP in conjunction with Encounter RTL Compiler technology.
DDR memory systems have emerged as a critical design requirement for
enabling high performance in virtually all electronics products, including
everything from cell phones to set top boxes. DRAM memory systems
require specialized tuning and tailoring to achieve specific performance
requirements for each unique design or application. The Databahn memory
controller uses simple synthesis script modifications combined with
Encounter RTL Compiler multi-objective optimization to achieve significant
advantages in area, speed and performance.
Encounter RTL Compiler global synthesis, a key technology of the Cadence
Encounter digital IC design platform, improves performance, reduces die
sizes, lowers power consumption, and speeds up design closure through place
and route. Cadence defines this metric as quality of silicon (QoS). This
ability to produce smaller, faster and cooler chips in less time has
increased customer competitiveness and reduced overall costs.
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