Cadence and MIPS Alliance
MIPS Technologies is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. MIPS designs and licenses the industry's highest performance 32- and 64-bit architectures and cores, which also offer some of the smallest silicon footprints and lowest power consumption of any embedded microprocessors.
Cadence® and MIPS collaborate to provide our mutual customers with a predictable path from RTL to first silicon. At nanometer geometries, SoC performance is dominated by the timing and noise behavior of a chip's routed wires. The Cadence Encounter™ Reference Methodology optimized for the MIPS 24K family provides an integrated, wire-centric RTL-to-GDSII core implementation for customers, fulfilling the objective to optimize the silicon design chain by providing better quality of silicon (QoS).
RTL-to-GDSII Reference Flow
The MIPS-Cadence Encounter RTL-to-GDSII Reference flow Methodology streamlines the development of designs based on the latest 24K MIPS processor. This powerful implementation flow, based on the Cadence Encounter digital IC design platform supports designs of up to 50M gates and provides a proven path for hardening the 24K processor and performing 24K-based designs. The Encounter platform enables a "wires first" approach to quickly create a detailed, full-chip, silicon virtual prototype—including routed wires—that allows designers to focus on critical issues. It includes a customized flow, a flexible GUI, the 24K reference design, and a base technology/library infrastructure. Validated synthesis and floorplanning scripts enable users to implement the latest technology quickly, with minimal ramp-up time.
Benefits
 | Increased design automation dramatically reduces tedious manual tasks and allows users to focus on design, not interoperability issues | | Customizable GUI offers a quick learning cycle for novice users and a flexible environment for expert users | | Predictable and repeatable results with Cadence First Encounter® rapid prototyping and optimized die sizing | | Superior QoS results ensure the fastest path to the best chip characteristics possible |
The optimized Cadence Encounter Reference Methodology is available to customers of the MIPS32 24K core family. Please contact MIPS Technologies for further information at +1 (650) 567 5000 or sales@mips.com.
|
|
 |
|
|
