CADENCE AND TSMC PARTNERSHIP
TSMC is the world's largest dedicated semiconductor foundry providing leading process technology and
the largest portfolio of process-proven libraries, IP, design tools, and reference flows. TSMC is a trusted partner for silicon manufacturing to both the smallest fabless start-up ventures and multi-national, multi-product companies.
Cadence has a broad and deep alliance with TSMC through the TSMC EDA, IP, and Design Center Alliance programs. Our Silicon Design Chain partnership is essential to first-pass silicon success for our mutual customers. Cadence and TSMC leverage the silicon readiness approach to design chain collaboration to characterize silicon,
validate IP and libraries, build and deliver comprehensive design kits and reference flows, and also deliver leading edge chips.
TSMC Reference Flow 8.0
TSMC and Cadence have collaborated on the industry's first 45nm TSMC Reference Flow. The
silicon-proven TSMC Reference Flow 8.0 integrates 45-nanometer readiness with new low-power
management techniques, advanced statistical static timing analysis (SSTA), and enhanced
design for manufacturing (DFM) and design for yield (DFY) capabilities. It allows designers
to accelerate advanced 45-nanometer design with lower power, faster cycle time, higher
quality and less manufacturing risk.
The Cadence contribution to TSMC Reference Flow 8.0 is based on several new capabilities
in the Cadence® Encounter® digital IC design platform and the Cadence Logic Design Team
Solution. The new capabilities are supported by Incisive® Design Team Simulator, Incisive
Enterprise Simulator as well as the Cadence SoC Encounter™ GXL RTL-to-GDS system.
The Reference Flow 8.0 delivers an RTL-to-GDS design flow that accelerates time to volume
for high-performance and low-power designs. The flow delivers a comprehensive methodology
to address complex design issues at 45 nanometers by providing advanced design techniques
to manage power consumption by:
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Addressing tighter manufacturing parameters
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Tackling an exponential increase in power leakage
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Meeting new extraction requirements to not only accurately predict the silicon behavior of an IC's interconnect but also to account for process variability at 45-nanometer process node
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These capabilities—described in the order of RTL to GDS—include support for the Si2 Common
Power Format (CPF) compliant low-power flow covering design, verification, implementation,
and analysis. The low-power flow enables new leakage-power reduction strategies such as Power
Shut Off (PSO). In the analysis category, process-variation extractions, thermal analysis
and thermal-aware leakage analysis address new dimensions of design careabouts. Reference
Flow 8.0 enables customers to prevent, detect and correct for yield limiters, as well as
to improve process windows and manage variations. Finally, the 45-nanometer-aware design
for test (DFT) features—such as power-aware ATPG, XOR compression—round out the highlight
of the Cadence solution. Additionally, this reference flow supports designs targeting TSMC's
Nexsys™ 45-nanometer process technologies.
As a supporting element of the TSMC Reference Flow 8.0, Cadence also provides entire
CPF-compliant 45-nanometer low-power tutorials and test cases, covering simulation,
design, implementation and analysis, based on the TSMC reference flow. Customers can
download these tutorials and test cases from TSMC-Online and observe the complete flow
in action using an actual design.
TSMC customers can also download technology files for Fire & Ice and Assura RCX; and rule decks for Assura, Dracula and Diva DRC/LVS at TSMC-Online.
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