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Cadence partner press releases

Press releases



07/09/08Power Forward Initiative Momentum Continues with Addition of Three Leading Japanese Design Services Companies
05/12/08VeriSilicon Joins Power Forward Initiative to Accelerate Advanced Low-Power Design
03/17/08Power Forward Initiative Releases Low-Power Design Methodology Guide
12/05/07Cadence and ARM Deliver Reference Methodologies for Multicore and Low-Power Devices
09/19/07Media Advisory: News Briefing to Focus on Successful Implementations of Advanced Low-Power Design Techniques
07/23/07Jazz Semiconductor Teams with Cadence on Support for Cadence RF and AMS Design Kits
06/06/07Cadence QRC Extraction Tool First to Qualify on TSMC's 45nm Process Technology
06/04/07Cadence Accelerates 45-nm Design With TSMC Reference Flow 8.0
04/10/07Call For Registration: Power Forward Initiative Panel Discussion At Date 2007, April 18, 2007, Nice, France
03/28/07TSMC 65-Nm Libraries First To Support Common Power Format-Enabled Design Flow
12/04/06Common Power Format Contributed by Cadence to SI2 Ahead of Schedule as a Result of Significant Customer Input
11/27/06Sirific Wireless readies two 3.5G RF transceivers for market using Cadence Logic Design technology
11/20/06Cadence Announces winners of the Collaborations Award for Excellence in Advancing Design Chain Alliances
11/01/06Cadence and Si2 Collaboration Paves the Way to a Unified Low-Power Standard
11/01/06Six New IP Providers Join Cadence OpenChoice; Expand IP Program to Enhance the Design Chain Ecosystem
10/25/06Media Advisory: Panel Discussion on Accelerating Low-Power Design with the Common Power Format, an industry-wide Collaboration
10/24/06ARM and Cadence Collaborate on Testability Requirements of ARM Partners with Encounter Test
10/05/06SI2's Low-Power Coalition to Have Access to Common Power Format
09/07/06Cadence and SMIC Deliver 90-Nanometer Low-Power Solution for Energy-Efficient SoCs
09/06/06Fujitsu Delivers ARM9E Processors for ASIC Designs Using Cadence Encounter RTL Compiler
09/05/06Power Forward Initiative Broadens Industry Support, Accelerates Standardization of Common Power Format
07/24/06Cadence and ARM Introduce First Automated Design and Implementation Flow for the ARM Cortex-A8 Processor
07/24/06Cadence, Magma, and Extreme DA Collaborate to Develop Industry Standard Library Format for Statistical Analysis Through SI2
07/20/06Media Advisory: Power Forward Initiative to Host an Open Forum Luncheon at 2006 DAC
07/20/06Power Forward Initiative Expands and Invites EDA Companies to Join Advisory Group
06/28/06Agere Systems Tapes Out Next-Generation, 90-nm Mobile Solution Chip Using Cadence X Architecture
06/28/06Denali's Databahn Memory Controller IP Supports Cadence Encounter Synthesis
05/25/06TSMC Production-Ready for 65-nm X Architecture Designs
05/25/06UMC Announces Readiness for 65-nanometer X Architecture Designs
05/22/06Cadence Unites Industry Leaders to Overcome Low-power Barriers for the Electronics Industry
05/17/06TSMC Adds Cadence Technologies for 65-Nanometer Design
05/15/06Cadence Releases Proven Reference Methodology for New ARM Cortex-R4 Processor
04/18/06Cadence and Teranetics Collaborate on Design of 10 Gigabit Ethernet Chips Using X Architecture
04/12/06SMIC and Cadence Deliver New Analog Mixed-Signal Reference Flow to Speed Fabless Chip Design
03/14/06IEEE Recognizes Cadence Leadership and Contributions to IEEE 1800 SystemVerilog Standard
03/01/06Cadence and CEVA Collaborate to Deliver Verification Process Automation to End Customers
02/07/06Cadence X Architecture Design Solution Wins 2006 IEC DesignVision Award
10/17/05Cadence Backs User Demand for Accelerating IEEE P1647 e Standardization
09/12/05ARM and Cadence Optimize Digital SOC Design Through Expanded Collaboration
09/08/05Cadence Announces Support for Industry-Standard OpenAccess 2.2 Database
08/24/05HiSilicon Technologies Collaborates With Cadence and SMIC to Produce Communications Device
07/25/05Accent, ARM and Cadence Collaborate to Improve Low-Power Design
06/14/05X Initiative Honors ATI and TSMC with Design-To-Manufacturing Catalyst Award
06/09/05Cadence Supports TSMC Reference Flow 6.0 to Accelerate 65-Nanometer Design
05/09/05Cadence and Faraday Announce Library Collaboration for Nanometer Design
03/22/05Cadence Contribution to Accellera Boosts Efforts to Standardize IC Design Kits for Designers
03/21/05Silicon Design Chain Collaboration Demonstrates Significant 90-nanometer Total Power reduction
02/28/05Cadence and Virage Logic Collaborate to Deliver Timing and Signal Integrity Views to Enable Low-Power Design
02/14/05Cadence Donates Technology to IEEE to Enhance SystemVerilog Usability
12/01/04Cadence Joins with IBM to Launch Power.org
12/01/04Azul Implements High-Speed Chip with Cadence Encounter
11/15/04Chartered and Cadence Qualify Fire & Ice QX for Leading-Edge Process Technologies
10/27/04Cadence and ARM Tackle Signal Integrity Issues for Foundry Program Partners with New Views
10/04/04Artisan and Cadence Collaborate to Optimize Low-Power Chip Design; New Library Views Support Next-Generation Low Power Devices
09/07/04UMC and Cadence Deliver Digital Reference Flow for Advanced Processes
08/31/04Shanghai Research Center for Integrated Circuit Design and Cadence Introduce New CPU/DSP Core-Based Methodology for SOC Chips
08/04/04Fujitsu Ties Global Partnership with Cadence to Create Advanced SoC Design Environments
07/15/04Cadence and Rambus Sign Agreements to Deliver Portfolio of High-speed Serial Link Solutions
06/07/04TSMC and Cadence Tackle Low Power Challenges at 90 Nanometers and Below with New TSMC Reference Flow
06/01/04Cadence and CoWare Deliver Electronic System-Level (ESL) Design-for-Verification Flow
04/19/04UMC and Cadence Deliver Analog Reference Flow for Mixed-Signal Designs
04/13/04TSMC Qualifies Cadence Encounter RTL Compiler for Next-Generation Reference Flow
04/05/04Cadence and MIPS Technologies Deliver Encounter Reference Methodology for Industry's Highest Performance 32-bit Core Family
02/16/04Cadence and ARM Upgrade Quality of Silicon Results for ARM Partners with RTL Compiler Synthesis
12/11/03Cadence Design Systems Awarded 2003 Strategic Supplier by Agere Systems
09/18/03Cadence and Chartered Team to Deliver Solutions for 90-nanometer IC Design
09/17/03ARM and Cadence Enable ARM Core-Based Designs Through the Silicon Design Chain
06/18/03Cadence Design Systems and Silicon Metrics Partner on Nanometer Delay Models
06/16/03Cadence Qualifies Reference Flow for IBM Nanometer Technology
06/02/03TSMC Employs Cadence Encounter Platform in New TSMC Reference Flow 4.0
04/22/03Cadence Teams with TeraChip to Deliver World's First 160Gbps Switch Fabric Chip
04/21/03Cadence Optimizes Design Chain for Xilinx Customers Using the 90nm Spartan-3 FPGA Platform
04/17/03Agere Systems and Cadence Design Systems Donate Chartreuse-II to VSI Alliance
03/04/03ARM and Cadence Establish New Five-Year Agreement Targeting Design Chain Optimization
03/03/03Cadence Joins the FlexRay Consortium
01/20/03Cadence and ATI Team to Form Broad Reaching Partnership
01/20/03IBM and Cadence Use Supercomputing Power of Linux in Leading Electronic Design Solutions
01/16/03Cadence Appoints Jan Willis Vice President of Strategic Third Party Programs; Willis to Lead Partnership Programs with EDA, IP, and Manufacturing Communities
01/13/03Now is the Time to Step Up and Support OpenAccess
01/13/03Cadence and TSMC Team to Accelerate Time-to-Volume for Nanometer Design; Cadence is First Full-Line Distributor of TSMC-Developed Libraries
12/16/02Cadence Delivers Source Code to OpenAccess Coalition
11/18/02Artisan Components and Cadence Team to Manage Nanometer Design Risk
09/30/02Cadence, IBM Team to Simplify Chip Design Process
08/19/02Cadence and UMC Partner to Enhance Nanometer Design for Manufacturability
07/22/02Cadence Speeds Design-to-Market for PolarFab Customers
07/15/02Cadence Speeds Communication Systems Design Chains
06/04/02Cadence and TSMC Announce Digital Flow Based on Cadence SoC Encounter
06/03/02Cadence Delivers Version 2 of the OpenAccess Database Source Code to the OpenAccess Coalition
06/03/02Quickturn Announces IP Program to Provide High-Speed Hardware/Software Co-Verification Environment for SoC Designs
05/28/02Cadence Delivers Verification Productivity Boost For Complex SoC Designs Through Commitment to Industry Standards
05/09/02Cadence And Credence Create Technology Alliance To Enable Open Design-To-Production Test Solutions
04/26/02Cadence Supports Accellera Standard
04/23/02Cadence And Ericsson Agree To Expand Strategic Relationship
03/25/02Chartered And Cadence Partner To Reduce Time-To-Market With Process Design Kit Offering
02/14/02Cadence And Agilent Technologies Strike Alliance To Speed Electronic Design In Wireless, Wireline Industries
02/04/02OPENACCESS COALITION RELEASES SOURCE CODE ROADMAP AND ANNOUNCES OPENCONNECT PROGRAM FOR DESIGN TECHNOLOGY INTEROPERABILITY
10/01/01Cadence And UMC Expand Partnership For Deep Submicron CMOS Designs
06/18/01Cadence Defines Vision to Address Design Chain Convergence Challenges
06/18/01OpenAccess Community, Si2 and Cadence Collaborate to Open Next-generation IC Design Infrastructure
04/25/01Cadence and PolarFab Collaborate to Accelerate Time-to-tapeout
03/12/01Cadence and Agere Announce Strategic Alliance to Develop Chip I/O Planning Capability
03/08/01Robert Bosch GmbH Selects Quickturn for Next-Generation In-Circuit Fault Emulation Projects
03/08/01Cadence And TSMC Collaborate To Distribute Design Kits For Baseband And RF Foundry Silicon
Cadence Supports TSMC Reference Flow 6.0 to Accelerate 65-Nanometer Design
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