Standards and Languages
One language can't solve all design and verification problems.
Different teams use different languages to take advantage of
the unique features each one provides. As a leader of open
standards, Cadence is dedicated to providing continuous support
for a variety of design and verification languages and
implementation standards.
For design and verification tasks, Cadence supports Verilog®,
VHDL,
SystemVerilog and the
Open Verification Methodology (OVM),
Property Specific Language (PSL),
SystemC®,
e , Verilog-AMS, and VHDL-AMS.
| Providing the best mix of languages for every specialist |
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For implementation tools, Cadence supports LEF, DEF, GDSII, SDF, SPEF, and the ECSM library format.
To date, Cadence has donated and made accessible to the industry more than a dozen major proprietary languages, formats, API specifications, and reference implementations, including Verilog, VHDL, SystemC, GDSII, SDF, LEF, DEF, ECSM, and OpenAccess.
To ensure unified standards for advanced design and verification, and to improve the process of turning specifications into fully implemented standards, Cadence is an active participant in Accellera and IEEE standards committees.
Our five industry-leading platforms are working proof of the Cadence® commitment to open standards:
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