Cadence SoC Functional Verification Kit
Functional verification of systems on chip (SoCs) has become one of the most time consuming and critical tasks in the development of complex processor-based integrated circuits. To reduce risk, achieve predictable verification closure, and deliver innovative products on time, engineers need automated verification process management, IP reuse, and the latest verification methodologies. The Cadence® SoC Functional Verification Kit addresses these challenges by providing higher levels of automation with reusable advanced verification techniques. It interactively integrates with the proven Cadence Incisive® Plan-to-Closure Methodology, reducing risk and delivering more efficient verification planning and execution.
The Cadence SoC Functional Verification Kit automates and eases the adoption of new verification technologies, increasing both productivity and predictability, from verification planning to closure. For the first time, design and verification teams can implement a proven methodology using an interactive flow-based approach. Rather than providing verification point-tools in isolation, the Kit delivers a combination of best-known principles, practices, and procedures—using all aspects of the industry-leading Incisive functional verification platform. The Kit consists of three primary flows of architecture, RTL block to chip, and system. The kit also integrates the Incisive Plan-to-Closure Methodology, design and verification IP, and hands-on workshops running on a real-world ARM-based SoC design—all delivered with expert consulting tailored to your specific verification challenges.
More than just a static paper snapshot of methodology, the Cadence SoC Functional Verification Kit is highly interactive with its own GUI navigator to jump-start the process by demonstrating how experts in verification developed and implemented advanced coverage-driven techniques. It's also modular, allowing companies to adopt the methodologies incrementally and focus only on the most critical portions of the project. The Kit addresses the verification of both hardware and software from block to chip to system levels, and low-power functional verification of the RTL. It guides engineers down a streamlined path from verification planning to closure.
Key benefits
 | Enables teams with varied experience levels to adopt advanced verification techniques in their designs with significantly reduced risk | | Restores schedule predictability through application of proven processes | | Eliminates common problems in advanced verification through expert knowledge and best practices | | Ensures product quality by verifying both hardware and software simultaneously at block, chip, and system levels | | Improves verification productivity with interactive understanding of methodology, verification IP re-use, and Incisive automation technology |
| Components of the Cadence SoC Functional Verification Kit |
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Kit Contents
| Wireless segment representative design (SRD) including (30) design blocks in different languages and levels of abstraction interconnected through a multi-layer AMBA® bus fabric | | Three primary flows of architecture, RTL block to chip, and system, supported by (13) workshops and (40+) hands-on labs | | Cadence and Kit-developed verification IP supporting both SystemVerilog and e testbench environments | | Interactive GUI navigator with hyperlinked interfaces to the Plan-to-Closure Methodology, best practices, and techtorials | | Detailed user guide documentation of the SRD and hands-on labs | | Expert consulting designed to apply the Kit's advanced methodologies to customer-specific challenges and design requirements |
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