Allegro Package Designer
Complete environment for concurrent co-design between IC and Package
Cadence Allegro® Package Designer products streamline IC package design and IC package co-design. They comprise a complete constraint-driven physical design solution that supports virtually all packaging methods as well as 3D viewing and 3D wirebond design rule checks The Allegro Package Designer combines chip-level I/O feasibility planning capabilities with industry-leading IC package tools to deliver a proven co-design methodology integrated with Cadence® First Encounter. This family of products also includes an embedded technology leading 3D field solver that allows engineers to quickly create full package-level simulation models that can help PCB designers trade off electrical performance versus size and cost. As performance targets for today's devices increase, demand for more accurate models grows. Cadence is committed to meeting those demands today and in the future. Key benefits
 | Allows users to determine best package and substrate technology early in IC design cycle | | Robust ECO flow and die editing tools support a true package-driven flow where the designer wants to optimize the I/Os at the die bump level to fit an existing package or to optimize a custom package | | Supports full package design flow from design capture through manufacturing output, supporting all the industry standards | | Integrates a design and analysis environment for making physical, electrical performance, and cost trade-offs easily and accurately | | Provides an embedded, proven 3D field solver avoids having to deal with design setup and difficult-to-use standalone post-layout analysis tools | | Integrates smoothly into the Cadence Encounter™ platform ECO flow via LEF/DEF | | Allows users to visualize, investigate, and wirebond DRC check an entire design, or selected design subset, reducing design cycle time and improving product manufacturability via Cadence 3D Design Viewer option |
Allegro Package Designer is available in the following configurations:
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Allegro Package Designer L
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Provides an entry-level configuration of the industry's leading design system for complete IC/package design. |
| Allegro Package Designer XL |
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Extends the L family to enable true IC and IC package co-design allowing designers of today's complex, leading-edge devices to meet cost, performance, and time-to-market goals. Includes chip-level I/O planning capabilities and an embedded 3D field solver. |
Cadence also offers a complete System-in-Package design technology for designers implementing multiple die, chips, or components into an IC package or system.
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| An integrated technology platform supports the VSIC model, IP availability, and silicon design-in technology |
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