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Silicon Design-In

Time to volume production for IC manufacturers depends on quick adoption of new devices by systems companies. However, the combination of differing design environments, complex I/O structures, and multigigabit-speed data rates make new device simulation and implementation into a PCB system a complex and expensive process.

Innovative silicon design-in IP portfolios from Cadence and key industry partners tackle these issues. Using technology available in the Allegro PCB SI design and analysis environment, IC manufacturers can help shorten their customers' design-in time on complex silicon devices by providing an executable version of their design guides in the form of high-speed silicon design-in IP portfolios. These silicon design-in IP portfolios allow engineers to accurately simulate PCB topologies with minimal setup, enabling them to obtain accurate simulation results 20 times faster than would have been possible without silicon design-in IP.

Cadence silicon design-in IP portfolios include the following:

Memory interfaces

	Cadence, Micron, Altera DDR2 Design-in IP
	Cadence, Altera, Elpida DDR2 Design-in IP

FPGA

	Altera Stratix GX Design-in IP
	Xilinx Virtex II-Pro Design-in IP

PCI Express Design Chain

	Intel PCB Design-in IP for 915 and 925X Express Chipsets
	Rambus design-in IP for PCI Express Raser PHY
	Altera Stratix GX Design-in IP for PCI Express

Processors

	Intel IXP2800 Network Processor Design-in IP
	Allegro PCB SI Design-in for Pentium III Xeon Processor at 700 and 900 MHz
	PCB SI Design-in IP for Itanium Processor Family

Press Releases

	Announces Availability of Design-in IP Portfolio for Memory Designs
	Cadence PCI Express Solution Passes PCI-SIG Compliance Testing
	Cadence Announces Availability of Design-in Kit for Intel IXP2800 Network Processor
	Xilinx and Cadence Solution Speeds Multi-Gigabit Designs for System Companies

Resources

	Silicon design-in IP datasheet
	Allegro PCB SI user community