IC-Package-PCB co-design
Cadence views IC packaging as the critical link in the IC-package-PCB design flow. Without this link, silicon design can end up difficult and expensive to implement in a system. Cadence® Allegro® IC/Package co-design technology moves chip/package co-design and analysis capabilities to a new level.
Products
 | Allegro Package Designer XL —provides chip-level I/O planning and co-design capabilities based on First Encounter® and embedded 3D field solver for full package-level simulation modeling | | Allegro Package Designer L—offers a constraint-driven layout environment for the physical design of complex, high-density IC packages | | Allegro Package SI L —tightly integrated SI solution for advanced IC packages; combines Allegro platform design environment and simulation technology with a proven 3D field solver engine from Optimal Corporation's PakSi-E product |
Related products
| Cadence 3D Design Viewer —full, solid model 3D viewer and 3D wirebond design rule checking (DRC) solution for complex IC package designs | | TSMC Reference Flow 7.0 — the Allegro platform is exclusively featured in TSMC Reference Flow 7.0 to optimize chip and package design flows. Includes new capability of handling simultaneous switching outputs in timing and IR drop analysis | | Virtuoso® Analog VoltageStorm® Option — when combined with Allegro Package SI L, this solution allows for IR drop analysis that considers the combined chip and package power delivery system |
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