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Virtuoso custom design success stories


Success Stories



Agere
Agere saves two months in design schedule using Virtuoso Layout Migrate

Cray Inc.
Cray Dramatically Accelerates Design Schedule Using Cadence Virtuoso Layout Migrate Solution

Epoch Microelectronics, Inc
Epoch Improves Accuracy Using Cadence RF Design Methodology Kit

Fujitsu VLSI Limited
Fujitsu Automates Standard Cell Migration Using Cadence Virtuoso Layout Migrate

Leopard Logic
Successful tapeout and first silicon for next-generation configurable logic device

Multigig
Multigig Implements Full Cadence-Based Simulation Flow for High- Precision RF and Mixed-Signal ICs

NemeriX
NemeriX Partners with Cadence VCAD Engineering Services Team to Meet Aggressive Power and Performance Goals for Next-Generation GPS Baseband IC

Realtek
Realtek Reduces Design Cycle Time on Communications SoC Using Virtuoso Transistor-Level to Full-Chip Mixed-Signal Verification

Saifun Semiconductors Ltd
Saifun Improves Productivty in Characterization Flow and Dramatically Reduces Runtime for IBIS Model Generation Using Virtuoso Spectre Circuit Simulator and Spectre MDL

Teradyne
Teradyne Improves Productivity and Quality of Silicon Using Cadence Virtuoso Multi-Mode Simulation

Archived success stories

Videos

Chris Silsby
Agilent Technologies
The Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.
RealMedia:Low (35K) | Med(100K) | High(250K)
Edwin Li, Ph.D.
Zeevo
Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules.
RealMedia:Low (35K) | Med(100K) | High(250K)
Steve Stern
Sipex
Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.
RealMedia:Low (35K) | Med(100K) | High(250K)
Thilo von Selchow
ZMD CEO
ZMD and Cadence Engineering Services work together to produce cutting edge ZigBee wireless solution
RealMedia:Low (35K) | Med(100K) | High(250K)
Toby Farrand
Chief Technical Officer, Digeo
Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.
RealMedia:Low (35K) | Med(100K) | High(250K)
Vincent Mouret
NemeriX
Cadence and NemeriX team up to produce industry leading GPS Chipset
RealMedia:Low (35K) | Med(100K) | High(250K)
Archived videos