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Home > Products > Design for manufacturing > Products > Cadence CMP Predictor
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Cadence CMP Predictor
Cadence® CMP Predictor is a powerful and flexible technology for
IC designers to identify potential yield issues and optimize the
performance of their designs. It provides full-chip, multi-level
interconnect thickness and topography predictions for copper ECD and
copper/dielectric CMP, so that any design can be manufactured at the
customer's foundry of choice.
CMP Predictor turns the uncertainty of process variation into predictable
impacts, and then minimizes and accounts for these impacts throughout the
design process. Using the CMP Analyzer Option, designers can identify
specific problem areas that affect yield, such as copper pooling.
Designers can also use CMP Predictor with RC extraction tools to
accurately identify timing-related problems (such as race conditions)
and to shrink today's increasing guardbands by eliminating the systematic
thickness variation component of the guardband.
CMP Predictor has been integrated with RC extraction design flows, such
as Cadence QRC Extraction, for sign-off applications. It has also been
integrated with hotspot detection, viewing, and fixing flows (Cadence Chip
Optimizer), which provides hints and automation to modify designs (primarily
through intelligent dummy fill) during post-route optimization.
Cadence CMP Predictor has been certified by most leading-edge IDMs and
foundries for their latest technology nodes, including IBM 65nm, TSMC
65nm, UMC 65nm, Chartered 65nm, and Samsung 65nm processes.
For more information on this product send an email to lisong@cadence.com.
Visit the Cadence Designer Network User Community for user contributed
technical articles, product reviews, and interactive forums. Visit
www.cdnusers.org.
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