Cadence Design Systems, Inc.

The capacitance, C, in Figure 1 is determined by measuring the difference in the drain current of the two inverters and deriving the value using the following equations:

Substituting capacitive current:

Results in this equation:

In these equations,

• T = time period of the pulses Vp and Vn
• f = frequency of the pulses
• V_dd = DC power supply
• i₁ = total drain current on left hand side (LHS) peudo inverter
• i₂ = total drain current on right-hand side (RHS) pseudo inverter

The current is normally in the pA to nA range and thus can easily be measured by a current meter. The equipment required for measuring the capacitance using COSMIC structures is:

• A dual pulse generator
• A current meter
• A DC power supply with low noise (microvolt range)

An oscilloscope is helpful for looking at the pulses being applied to the gates of the pseudo inverter but not required.

Since the reference structures were first published by U.C. Berkeley in 1996, changes have been made to the methodology enabling whereby not only total capacitance but also coupling capacitance can be measured between any two lines in the presence of any other lines.

The COSMIC methodology has been used and tested to measure total capacitance of a line in the presence of any other lines for any process down to 90nm technology node. In addition, the methodology has been extended to measure coupling capacitance of any two lines in the presence of any other lines. As an example, Table I shows measured coupling capacitances using COSMIC approach for 180nm Al process. The measured data is compared with field solver and full-chip parasitic extractor Fire & Ice®. The results validated Fire & Ice to be within 10% of silicon. Note that structures A, B and C are inter-digited lines, two parallel lines, and two crossing lines, with different line width and spacing.

To decrease interconnect delay, copper and low k dielectrics have been introduced at 130nm mode to reduce interconnect resistance and coupling capacitance. Manufacturing effects such as wide edge enlargement (WEE) and pattern density dependent metal width and thickness variations etc. have made modeling and characterization of capacitance become difficult. Therefore COSMIC has been enhanced to provide coupling capacitance extraction that takes above manufacturing effects into consideration, and at atto-farad level accuracy, enabling accurate interconnect extraction verification at advanced process nodes. Since COSMIC enables capacitance measurement between two lines in the presence of any other lines, by using comb type test structure between the two metal plates (see Figure 2), the non-ideal trapezoidal Cu metal line widths at the top (Wt) and bottom (Wb) surfaces can be measured electrically.

Figure 2. Inter-digital metal lines between metal plates

Inter-digited metal lines (shown here as 2-D cross-section) sandwiched between metal plates on the top and bottom. COSMIC measures C_c, C_t and C_b, from where we can find W_t, W_b, S_t, S_b and T.