Cadence Design Systems, Inc.

Technical Info

This page contains technical information related to Design for manufacturing, including application notes, white papers, and articles.

White papers

	Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation

	Model-based Methods Critical for Effective Manufacturing-aware Physical Design

	Next-Generation Signoff Analysis Tackles Electrical, Physical, And Manufacturing Challenges

	Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs

	AMD/Clear Shape: Automated Full-Chip Hotspot Detection and Removal Flow for Interconnect Layers of Cell-Based Designs

more white papers

Articles

05/06/08	DRC signoff doesn't cut it for next-gen nodes

03/05/08	Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM

02/11/08	SPIE and the IC design world: a wall starts coming down

10/08/07	Signoff for Manufacturability

09/24/07	Cadence DFM - WYDIWYG; Interview with Mike McAweeney

more articles

Cadence feature stories

09/10/07	New Cadence Flow Enables Fast, Accurate Design and Manufacturing of Advanced ICs

04/20/07	Latest Encounter Platform Offers New DFM and Low-Power Features for 65nm Designs

04/06/07	Cadence Space-Based Router Wins 17th Annual EDN Innovation Award for Best IC Back-End and DFM Product

02/10/06	Virtuoso RET Suite Integrates Lithography Awareness Into Industry-Leading Layout Environment

10/14/05	Cadence Physical Verification System Sets New Standard for Design Signoff