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Home > Products > Encounter digital IC design > Products > CeltIC NDC
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CELTIC NDC
Signal integrity (SI) is a growing concern for designers of cell-based digital ICs. SI effects such as crosstalk and IR drop affect both timing and functionality, and can result in lower chip performance, dead chips, or poor yield.
CeltIC® (nanometer delay calculator) NDC is an SI-aware nanometer delay calculator that provides you with a unified timing solution that accurately accounts for the impact of crosstalk and IR drop on both delay and functionality. Part of the Cadence® Encounter® digital IC design platform, CeltIC NDC helps you weed out false SI failures quickly and more than 10 to 100 times more accurately than other solutions. This, in turn, reduces design iterations and saves valuable chip area.
Building on the strengths of customer-trusted CeltIC NDC technology, Encounter Timing System takes timing and SI to a new level. It offers a new full-chip, gate-level timing/SI analysis and signoff solution that boosts your productivity and ensures accuracy for the largest and most complex designs.
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