Cadence Kits
Incisive functional verification
Encounter digital IC design
PRODUCTS
SoC Encounter
First Encounter
Encounter RTL Compiler
Encounter Test
Encounter Conformal ECO Designer
Encounter Conformal Equivalence Checker
Encounter Conformal Constraint Designer
Encounter Conformal Low Power
Encounter Timing System
Encounter Library Characterizer
CeltIC NDC
NanoRoute
VoltageStorm
Cadence QRC Extraction
Cadence Chip Optimizer
Cadence SiP Digital Architect
Cadence SiP Digital Layout
Cadence SiP Digital SI
DESIGN TASKS
High-performance timing closure
Implementation of large-scale designs
Analysis and signoff
Design for Manufacturing
Mixed-signal design
Applications Using the ARM Cortex-A8 Processor
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
IP catalog
Print-friendly version
Encounter Conformal Constraint Designer

Download PDF datasheet

To shorten overall design-cycle times and minimize silicon re-spins, designers need production-proven validation. Encounter® Conformal® verification technologies, part of the Cadence® Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution, offer the most comprehensive solutions for equivalence checking, design-constraint management, functional ECO, and low-power design verification

Encounter Conformal Constraint Designer automates the generation, validation, and refinement of constraints to ensure that SDC constraints and timing exceptions are valid throughout the entire design process, helping designers to reduce iterations and accelerate timing closure. Encounter Conformal Constraint Designer is available in L and XL offerings.

Visit the Cadence Designer Network User Community for user contributed technical articles, product reviews, and interactive forums. Visit www.cdnusers.org.

Read Encounter customer success stories and find out how others are succeeding with Encounter technology.

Encounter Conformal Flow
Encounter Conformal Flow


Find out how a CPF-enabled methodology can help reduce power consumption on your next chip
Plan-to-closure methodology
What's new

Encounter RTL Compiler wins EE Times Synthesis Poll
Encounter RTL Compiler was the clear favorite EDA synthesis tool in a recent poll of EE Times Europe readers.

Analysis and signoff
The most comprehensive and accurate analysis and signoff solution bringing together logical, physical, electrical, and manufacturing domain requirements in a single, easy-to-use environment.

Resource library
 

Datasheets
Platform brochure (PDF)
Demos and webinars
Technical info
Success stories
Release info
News and events
User community
TSMC Libraries

Support and services
 

Engineering services
SourceLink
Education
Downloads

Request Information