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Home > Products > Encounter digital IC design > Design tasks > Design for Manufacturing
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Design for Manufacturing
As process nodes shrink to 65nm and 45nm, designers must consider a wider range of process effects on manufacturability, such as device and interconnect sensitivity due to different temperatures and multiple process corners, 3-D layer density variation that may affect chemical mechanical polishing, and imperfections in the lithographic process. Such long-range variations and unpredictable effects can severely affect circuit performance in silicon and put even more strain on your physical implementation methodologies.
To achieve high-yield goals quickly, designers must make tradeoffs among timing, area, power, and yield. The SoC Encounter™ system offers accurate modeling of variations and critical area analysis based on the process technology node up front, helping you make the best design and implementation decisions.
Embedded in SoC Encounter GXL is a full array of CMP- and lithographically-aware yield enhancements, such as high-yield cell optimization, double cut via insertion, interconnect widening and spreading, and density uniformity optimization. These capabilities enable concurrent implementation and post-process optimizations that carry out your tradeoff decisions consistently, so you can minimize iterations and maximize yield from prototyping through signoff.
Cadence has been collaborating continuously with leading library providers, integrated device manufacturers (IDMs), and silicon foundries to ensure realization of first-silicon success at 65nm and 45nm nodes. SoC Encounter GXL's design-for-manufacturing and design-for-yield technologies are validated and qualified by leading IDM customers and foundry reference flows.
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