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Home > Products > Encounter digital IC design > Design tasks
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Encounter digital IC design platform design tasks
|  | High-performance timing closure
The demand for applications to run faster imposes severe restrictions on clock periods. At the same time, process technologies are so sophisticated that variability has become a major concern. Traditional guard banding of design constraints no longer works to achieve timing closure.
Cadence Encounter technologies address the four critical issues that designers face when trying to achieve timing closure on high-performance designs:
- Timing closure in the presence of on-chip variation
- Capacity and runtime with large designs
- Early predictability of performance
- Concurrent handling of timing, area, and power
Encounter technologies are built on a newer paradigm to enable concurrent handling of multiple constraints. They also work on "correct-by-construction" methodologies that help you reach convergence faster. Advanced Encounter timing closure solutions handle on-chip variation through multi-mode and multi-corner analysis, robust clock tree synthesis, and powerful globally focused optimization. They also provide early predictability of design performance through silicon virtual prototyping and promote a "continuous convergence" approach to design.
| | | Implementation of large-scale designs
Implementation of large-scale designs can be time-consuming and costly. Nanometer technologies enable mass integration of functionality, but they also increase timing sensitivity, yield variation, and leakage power. Up against late design-cycle surprises, designers are forced to iterate or, worse yet, sacrifice design quality.
The "divide-and-conquer" approaches of the past are insufficient. Physical designers feel like they're manufacturing engineers. Logic designers feel like they're physical engineers. And test engineers are being drawn into both physical and logical issues. Cadence® Encounter® implementation technologies provide you with a scalable and integrated environment for more efficient and cost-effective implementation of large-scale designs.
Silicon virtual prototyping: First Encounter® technology pioneered the use of virtual prototyping for early physical design feedback, and it remains the standard for early "big chip" exploration. With virtual prototyping, you can create more accurate block-level constraints, get an early picture of top-level timing, congestion, and power problems, and make more intelligent selections of IP and packages. These capabilities reduce iterations and surprises.
Global concurrent optimization: Encounter RTL Compiler allows you to look across your entire design as you employ concurrent optimization techniques, such as making tradeoffs among timing, area, power, and signal integrity. New physically-aware layout estimation and quality of silicon models increase the accuracy of full-chip wireload estimates to help you eliminate costly mistakes.
DFM-aware routing: NanoRoute® Ultra and Cadence Chip Optimizer shift design-for-manufacturing (DFM) awareness into the implementation phase, where you can maximize changes at minimal cost. NanoRoute Ultra optimizes routing for signal integrity, timing, and DFM while still maintaining the utmost in speed and capacity. Cadence Chip Optimizer squeezes out the last points of yield with its new hierarchical space-based architecture. It performs full interconnect optimization and last-minute engineering changes — all within a DFM-, timing-, and connectivity-aware environment.
Integrated validation and cross-referencing: Conformal® technologies (Equivalence Checker and Constraint Designer) provide you with a scalable solution for validating and cross-referencing netlist and constraint changes as you move through the implementation flow. Constraint validation and logic structure identification is no longer a tedious chore — what took weeks now takes only days.
Integrated full-chip test insertion: Encounter Test Architect brings an unprecedented productivity boost to large-chip test insertion. It's the only compiler-driven solution that integrates disparate test structures into a signal insertion flow. I/O, Bist, and scan-test insertions can be automated, eliminating costly scripting errors and delays.
| | | Analysis and signoff
The Cadence Digital Implementation Solution delivers the most comprehensive
and accurate analysis and signoff solution. It brings together logical, physical,
electrical, and manufacturing domain requirements in a single, easy-to-use
environment, enabling front-end to back-end design handoff, signoff-driven
implementation, and final signoff. The Cadence Digital Implementation Solution
offers a complete debug environment for timing, signal integrity, power, concurrent
multi-corner, statistical, electromigration, and thermal analysis. It allows for
quick and easy multi-dimensional root-cause analysis to reach design closure and
time-to-volume production much faster. Designers can prevent silicon failures and
better manage variations—across both a wafer and the surface of a single chip.
| | | Design for Manufacturing
As process nodes shrink to 65nm and 45nm, designers must consider a wider range of process effects on manufacturability, such as device and interconnect sensitivity due to different temperatures and multiple process corners, 3-D layer density variation that may affect chemical mechanical polishing, and imperfections in the lithographic process. Such long-range variations and unpredictable effects can severely affect circuit performance in silicon and put even more strain on your physical implementation methodologies.
To achieve high-yield goals quickly, designers must make tradeoffs among timing, area, power, and yield. The SoC Encounter® system offers accurate modeling of variations and critical area analysis based on the process technology node up front, helping you make the best design and implementation decisions.
Embedded in SoC Encounter GXL is a full array of CMP- and lithographically-aware yield enhancements, such as high-yield cell optimization, double cut via insertion, interconnect widening and spreading, and density uniformity optimization. These capabilities enable concurrent implementation and post-process optimizations that carry out your tradeoff decisions consistently, so you can minimize iterations and maximize yield from prototyping through signoff.
Cadence has been collaborating continuously with leading library providers, integrated device manufacturers (IDMs), and silicon foundries to ensure realization of first-silicon success at 65nm and 45nm nodes. SoC Encounter GXL's design-for-manufacturing and design-for-yield technologies are validated and qualified by leading IDM customers and foundry reference flows.
| | | Mixed-signal design
With the number of analog and mixed-signal blocks in today's SoC designs rapidly increasing, engineers need advanced capabilities and flows for handling such blocks in predominantly digital designs — without loss of productivity or increase in turnaround time.
At the floorplanning stage, placement needs to be aware of analog/mixed-signal blocks and their interaction with digital blocks. Critical signals, power requirements, and I/O cells need special attention. Floorplanning technologies must be aware of noise-generating and noise-sensitive circuitry and assist designers with making tradeoffs to minimize probability of chip failure.
At the integration phase, routing top-level nets often requires capabilities like differential pairs, matched length/resistance, shielding (including coaxial), and bus routing. Extraction must obtain parasitics for such nets and pass them to analysis for final verification. Analog/mixed-signal simulation can then be used to verify interfaces between analog and digital parts.
| | | Applications Using the ARM Cortex-A8 Processor
Designing with embedded processors, such as the ARM® Cortex™-A8 processor, for low-power mobile and consumer applications presents a number of challenges including shrinking geometries and power efficiency. It also requires large numbers of designers and months of design time. |
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