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Home > Products > Encounter digital IC design > Products > Encounter Test
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Encounter Test
Encounter® Test, a key technology in the Cadence® Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution, provides the industry's most advanced test solution from RTL to silicon. Based on breakthrough timing-aware and power -aware technologies, Encounter Test enables customers to manufacture higher-quality power-efficient silicon, faster and at lower cost.
Integrated with Encounter RTL Compiler global synthesis, Encounter Test inserts a complete test infrastructure to assure high testability while reducing the cost-of-test with on-chip test data compression. Using the inserted test infrastructure, Encounter True-Time Test automatically generates the highest coverage tests to uncover small delay defects common in today's nanometer designs. To speed yield ramp, Encounter Diagnostics analyzes results from manufacturing test to find systematic failures and pinpoint their location within the design layout.
To support manufacturing test of low-power devices, Encounter Test uses power intent information to create distinct test modes automatically for power domains and shut-off requirements. It also inserts design-for-test (DFT) structures to enable control of power shut-off during test. The power-aware ATPG engine targets low-power structures, such as level shifters and isolation cells, and generates low-power scan vectors that significantly reduce power consumption during test. Cumulatively, these capabilities minimize power consumption during test while still delivering the highest quality of test for low-power devices.
Encounter Test also supports XOR-based compression architecture to allow a mixed-vendor flow, giving you more flexibility and options to control test costs. It works with all popular design libraries and automatic test equipment (ATE).
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Products
Encounter Test Architect's power-aware unified methodology for specifying, inserting, and verifying high-quality, power efficient, full-chip tests helps logic design teams minimize cost-of-test for hierarchical and flat nanometer designs. Encounter Test Architect is available in L, XL, and GXL offerings.
Encounter True-Time Test provides timing-aware and power-aware ATPG engines that detect small delay defects. It supports stuck-at and transition fault models and it raises the bar by providing defect-based modeling capability with its patented pattern fault technology. Encounter True-Time Test is available in L, XL, and GXL offerings.
Encounter Diagnostics is a complete, intuitive, full-function solution for ramping yield on 65nm devices. Its highly accurate engine, volume analysis environment, and physical layout browsing capability help engineers quickly analyze thousands of failures, identify the source of systematic yield loss, and accurately pinpoint defect location in the netlist and layout. Encounter Diagnostics is available in L, XL, and GXL offerings.
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