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Home > Products > Encounter digital IC design > Products > Encounter Timing System
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Encounter Timing System
Successful digital chip design hinges on timing closure—and timing closure depends on accurate, correlated signoff-quality timing throughout implementation, optimization, and analysis. Conventional solutions require one or more timing engines for implementation and another for signoff analysis. But in sub-90nm design, multi-dimensional variables make a single view of timing essential.
Encounter® Timing System offers a consistent, integrated static timing analysis (STA) environment for place-and-route optimization and signoff verification. This leads to faster convergence and design closure, and it gives you the flexibility to use Encounter Timing System as a standalone solution or as part of the integrated Cadence® SoC Encounter™ RTL-to-GDSII system.
Encounter Timing System is available in L, XL and GXL offerings.
Complete view of timing
Encounter Timing System serves both front-end logic designers looking for high-quality timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff. It combines CeltIC NDC's production-proven signal integrity (SI) analysis capabilities with Cadence technologies for timing and power analysis, delay calculation, advanced modeling, and statistical and thermal analysis. And because it handles industry-standard Liberty and SDC formats, Encounter Timing System offers unprecedented usability and ease of adoption.
Global timing debug and ECSM
Global timing debug helps you pinpoint the root cause of timing and constraint issues at the push of a button. Through intelligent debugging of more than just the worst path and sequential analysis, Encounter Timing System eliminates corrective iterations. It also ensures accuracy and performance with sophisticated delay calculation. Using the effective current source model (ECSM) for advanced timing, power, and statistical delay modeling, Encounter Timing System delivers the most accurate prediction of actual silicon performance and shaves weeks off tapeout schedules, giving you a competitive edge over traditional delay modeling.
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