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Home > Products > Encounter digital IC design > Products > First Encounter
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First Encounter Silicon Virtual Prototyping
With shrinking geometries, increasing design sizes, and evermore complex SoCs,
the technical challenges of numerous hard macros, various clock speeds, leakage
currents, and flip-chip are enormous. Designers need to assess the feasibility
of these larger, faster, power-hungry designs with narrower time-to-market
windows and less time to get from RTL to GDSII. To solve this schedule predictability
crisis, design teams require faster placement, routing, timing, and power closure,
and they need a prototyping methodology that eliminates implementation iterations
and late design-cycle surprises. At the same time, they need to use flip-chip to
improve their chip performance, turnaround time, and cost.
First Encounter® Silicon Virtual Prototyping, part of the Cadence® Encounter® digital
IC design platform, brings more predictability to the design cycle. It provides a clear
path to synthesize to a full-chip virtual prototype and helps analyze full-chip routing
effects—right at the beginning of the design cycle. First Encounter technology spans
silicon virtual prototyping, automatic floorplanning, complete power-grid realization,
hierarchical partitioning and budgeting, and hierarchical clock-tree synthesis for high
performance on designs implemented in sub-90nm process technologies. It supports multiple
flip-chip methodology with automatic 45-degree RDL routing and it includes low-power and
yield capabilities to support advanced 65nm design. With First Encounter technology,
customers can meet their time-to-market requirements with significant performance and
productivity gains.
First Encounter Silicon Virtual Prototyping is available in L, XL, and GXL offerings.
Benefits:
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Delivers a silicon-proven solution that combines the power of silicon virtual
prototyping with a global physical synthesis (GPS) algorithm to achieve timing
closure on complex designs
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Performs fast, accurate, and flexible feasibility analysis
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Automated floorplan synthesis and ranking system enables rapid exploration
of the design space with handoff to the physical implementation flow and
provides a predictable path to design closure
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Offers a high-capacity, high-throughput, integrated solution to address the largest
designs while achieving huge productivity gains
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Handles 50M+ gate designs in sub-130nm process technologies
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Supports multiple implementation styles with built-in fast power planning,
relative floorplanning, and signal integrity analysis
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Supports multiple methodologies for flip-chip implementation with automatic RDL
routing and 45-degree support, enabling the concurrent chip/package design
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