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Home > Products > Encounter digital IC design > Design tasks > Implementation of large-scale designs
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Implementation of large-scale designs
Implementation of large-scale designs can be time-consuming and costly. Nanometer technologies enable mass integration of functionality, but they also increase timing sensitivity, yield variation, and leakage power. Up against late design-cycle surprises, designers are forced to iterate or, worse yet, sacrifice design quality.
The "divide-and-conquer" approaches of the past are insufficient. Physical designers feel like they're manufacturing engineers. Logic designers feel like they're physical engineers. And test engineers are being drawn into both physical and logical issues. Cadence® Encounter® implementation technologies provide you with a scalable and integrated environment for more efficient and cost-effective implementation of large-scale designs.
Silicon virtual prototyping: First Encounter® technology pioneered the use of virtual prototyping for early physical design feedback, and it remains the standard for early "big chip" exploration. With virtual prototyping, you can create more accurate block-level constraints, get an early picture of top-level timing, congestion, and power problems, and make more intelligent selections of IP and packages. These capabilities reduce iterations and surprises.
Global concurrent optimization: Encounter RTL Compiler allows you to look across your entire design as you employ concurrent optimization techniques, such as making tradeoffs among timing, area, power, and signal integrity. New physically-aware layout estimation and quality of silicon models increase the accuracy of full-chip wireload estimates to help you eliminate costly mistakes.
DFM-aware routing: NanoRoute® Ultra and Cadence Chip Optimizer shift design-for-manufacturing (DFM) awareness into the implementation phase, where you can maximize changes at minimal cost. NanoRoute Ultra optimizes routing for signal integrity, timing, and DFM while still maintaining the utmost in speed and capacity. Cadence Chip Optimizer squeezes out the last points of yield with its new hierarchical space-based architecture. It performs full interconnect optimization and last-minute engineering changes—all within a DFM-, timing-, and connectivity-aware environment.
Integrated validation and cross-referencing: Conformal® technologies (Equivalence Checker and Constraint Designer) provide you with a scalable solution for validating and cross-referencing netlist and constraint changes as you move through the implementation flow. Constraint validation and logic structure identification is no longer a tedious chore—what took weeks now takes only days.
Integrated full-chip test insertion: Encounter Test Architect brings an unprecedented productivity boost to large-chip test insertion. It's the only compiler-driven solution that integrates disparate test structures into a signal insertion flow. I/O, Bist, and scan-test insertions can be automated, eliminating costly scripting errors and delays.
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