With the number of analog and mixed-signal blocks in today's SoC designs rapidly increasing, engineers need advanced capabilities and flows for handling such blocks in predominantly digital designs—without loss of productivity or increase in turnaround time.
At the floorplanning stage, placement needs to be aware of analog/mixed-signal blocks and their interaction with digital blocks. Critical signals, power requirements, and I/O cells need special attention. Floorplanning technologies must be aware of noise-generating and noise-sensitive circuitry and assist designers with making tradeoffs to minimize probability of chip failure.
At the integration phase, routing top-level nets often requires capabilities like differential pairs, matched length/resistance, shielding (including coaxial), and bus routing. Extraction must obtain parasitics for such nets and pass them to analysis for final verification. Analog/mixed-signal simulation can then be used to verify interfaces between analog and digital parts.
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