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Encounter RTL Compiler
Encounter Test
Encounter Conformal ECO Designer
Encounter Conformal Equivalence Checker
Encounter Conformal Constraint Designer
Encounter Conformal Low Power
Encounter Timing System
Encounter Library Characterizer
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NanoRoute
VoltageStorm
Cadence QRC Extraction
Cadence Chip Optimizer
Cadence SiP Digital Architect
Cadence SiP Digital Layout
Cadence SiP Digital SI
DESIGN TASKS
High-performance timing closure
Implementation of large-scale designs
Analysis and signoff
Design for Manufacturing
Mixed-signal design
Applications Using the ARM Cortex-A8 Processor
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
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Encounter RTL Compiler Synthesis

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To maximize performance, decrease die size, reduce power consumption, and boost productivity, designers need a global synthesis solution that enables concurrent optimization of timing, area, and power.

Encounter® RTL Compiler, a key technology in the Cadence® Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with new physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon.

Read about a number of key adoptions and customer successes that have established Encounter RTL Compiler as the industry leader in global synthesis technology.

Visit the Cadence Designer Network User Community for user contributed technical articles, product reviews, and interactive forums. Visit www.cdnusers.org.

Read Encounter customer success stories and find out how others are succeeding with Encounter technology.

Encounter RTL Compiler
Encounter RTL Compiler


Find out how a CPF-enabled methodology can help reduce power consumption on your next chip
Plan-to-closure methodology
What's new

Encounter RTL Compiler wins EE Times Synthesis Poll
Encounter RTL Compiler was the clear favorite EDA synthesis tool in a recent poll of EE Times Europe readers.

Analysis and signoff
The most comprehensive and accurate analysis and signoff solution bringing together logical, physical, electrical, and manufacturing domain requirements in a single, easy-to-use environment.

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