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Home > Products > Encounter digital IC design > Success stories
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Digital IC Design success stories
Success Stories
Accent
Companies validate low-power design techniques from architecture through implementation to enable 40% power reduction
Celestial Semiconductor
Cadence Encounter Platform Helps Celestial Develop High-Speed Multimedia IC Based on 130nm Process
Cray Inc.
Cray Meets Aggressive ASIC Design Schedule, Leveraging Results from Encounter Test to Accelerate System Bring-Up
Digeo
Cadence Encounter Platform and VCAD Services Deliver 1st Silicon Success
F5 Networks, Inc.
F5 Networks Saves 25% on Power and 12% on Area Using Cadence Encounter RTL Compiler
Inphi corporation
Inphi Achieves Timing Closure and 1st Silicon Success? Using Encounter RTL Compiler Global Synthesis and SoC Encounter RTL-to-GDSII System
Layer N Networks
Incisive and Encounter platforms enable front-to-back complex SoC design
NemeriX
NemeriX Partners with Cadence VCAD Engineering Services Team to Meet Aggressive Power and Performance Goals for Next-Generation GPS Baseband IC
NetEffect
Cadence Solution Helps NetEffect to Dramatically Improve Network Performance and Interoperability
Renesas
Cadence Encounter Timing System Helps Renesas Reduce "Pessimistic" Compensation in 65nm and Below Designs
TeraBlaze
Encouncer RTL Compiler Enables Faster Time to Quality of Silicon For Complex ASIC Design
Toshiba America Electronic components, Inc.
Designing the fastest 100% synthesizable 64-bit MIPS CPU core
Via Telecom, Inc.
VIA Telecom Leverages Cadence to Perform Full-chip Verification
ZMD on Cadence Encounter platform and VCAD services
ZMD and Cadence work together to produce cutting edge, low power ZigBee solution
Archived success stories »
Encounter RTL Compiler successes »
Customer success quotes »
| Videos | |  |
 | | Amit Chandra
Sr. Engineering Manager, P.A. Semi
Amit Chandra talks about using the Encounter platform to overcome high-performance, low power design challenges.
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High(250K) | | | |  | | Bret Zahn
Vice President, Design and Characterization, ChipPAC
Cadence IC Packaging solutions help ChipPAC increase communication and easily pass designs between designers around the world.
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High(250K) | | | |  | | Bruce Cory
DFT Methodology Manager, nVidia
Bruce Cory talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.
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High(250K) | | | |  | | Chris Malachowsky
nVidia
nVidia VP of Engineering Chris Malachowsky talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help nVidia get results.
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High(250K) | | | |  | | Dan Dobberpuhl
President and CEO, P.A. Semi
Dan Dobberpuhl talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.
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High(250K) | | | |  | | Greg North
Chief Technology Officer and VP of Engineering, Luminary Micro
Greg North talks about using the Encounter platform to overcome nanometer design challenges.
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High(250K) | | | |  | | Martin Spohr
Senior Engineer, NEC Electronics
Martin Spohr talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.
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High(250K) | | | |  | | Thilo von Selchow
ZMD CEO
ZMD and Cadence Engineering Services work together to produce cutting edge ZigBee wireless solution
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Archived videos
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