The demand for applications to run faster imposes severe restrictions on clock periods. At the same time, process technologies are so sophisticated that variability has become a major concern. Traditional guard banding of design constraints no longer works to achieve timing closure.
Cadence® Encounter® technologies address the four critical issues that designers face when trying to achieve timing closure on high-performance designs:
Timing closure in the presence of on-chip variation
Capacity and runtime with large designs
Early predictability of performance
Concurrent handling of timing, area, and power
Encounter technologies are built on a newer paradigm to enable concurrent handling of multiple constraints. They also work on "correct-by-construction" methodologies that help you reach convergence faster. Advanced Encounter timing closure solutions handle on-chip variation through multi-mode and multi-corner analysis, robust clock tree synthesis, and powerful globally focused optimization. They also provide early predictability of design performance through silicon virtual prototyping and promote a "continuous convergence" approach to design.
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