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Home > Products > Incisive functional verification > Products > Testbench automation
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Incisive Testbench Automation
Verification is often the bottleneck in delivering today's highly
integrated electronic systems and chips. Part of Cadence® Incisive®
functional verification technology, Incisive Enterprise Specman products blend
leading-edge process automation with the comprehensive Incisive
Plan-to-Closure Methodology
to simplify and speed verification. Specman® products automate
the entire verification process from individual blocks to the full
chip and all the way to the project level, increasing productivity
and delivering a predictable path to high-quality silicon.
Specman products enable use of the powerful e verification language
to capture rules from executable specifications and then use this
information to automate verification. By eliminating misrepresentations
of specifications, the Specman methodology finds even the most subtle
corner-case bugs. Additionally, since support for IP reuse is built-in,
Specman products leverage existing investments while also producing higher
quality products in less time.
Specman products now include the following productivity components for rapid environment construction:
Incisive Scenario Builder: enables non-verification specialists to
create reusable sequences and multi-channel test cases on top of an
e
verification environment; requires no training in verification techniques;
uses a simple drag-and-drop test-building interface, cutting the time
to first test from days to hours.
Incisive Verification Builder: a GUI-based "wizard" supports the rapid configuration
of existing Incisive Universal Verification Components (UVCs) or the quick construction
of all-new UVCs
Incisive e Analyzer: a GUI-based static analysis and methodology enforcement tool
View tech brief 
The functionality of Specman core technology can be extended with Incisive
Specman ESL Testbench, which provides a high-throughput channel between the
testbench and the design under test (DUT). It also enables Plan-to-Closure
verification automation of embedded software exactly as if it were another part
of the DUT. Integrated with other Incisive technologies—including verification
IP, hardware acceleration and emulation, analog/mixed-signal/RF verification,
and formal assertion verification—Specman products support any testbench, HDL,
software, or assertion IP.
Incisive Testbench Automation is compatible with the
Open
Verification Methodology (OVM) and the e
Reuse Methodology (eRM).
Key benefits
 | Captures executable specifications and eliminates misrepresentations | | Uses constraints to automate test generation | | Speeds debugging with data and assertion checking | | Increases predictability with functional coverage analysis | | Supports e and SystemC® languages, plus C, VHDL, Verilog®, and SystemVerilog | | Enables hardware/software co-verification | | Integrates with all leading HDL simulators and supports a high-performance, direct kernel interface to all Incisive simulators |
Resources
EDA DesignLine article: Rigorous Automated Verification Yields High Quality Silicon
Chip Design article: Coverage-Driven Methodology for SoC Development Critical for Success
Chip Design article: Metric-driven Methodology Speeds the Verification of a Complex Network Processor
Design & Reuse article: e Verification Environment for FlexRay Advanced Automotive Networks
EE Times article: Software extensions to functional tools handle co-verification in SoCs
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